mpc8xx_lo.s

motorola 针对coldfire 5275 评估板的Dbug bootloader源程序

    #
    # File:     mpc8xx_lo.s
    #
    # Purpose:  Lowest level routines for all MPC8XX dBUG
    #
    # Notes:    This file assembles with both Diab and GNU assemblers
    #
    #
    # Modificiations:
    #
    #

    # Globally accessible symbols
    .extern VECTOR_TABLE

    .global asm_startmeup           # Called by dBUG RESET command
    .global asm_exception_body
    .global asm_isr_handler
    .global asm_switch_context
    .global asm_sc_exit_to_dbug
    .global asm_return_from_call

    .global cpu_iord_8
    .global cpu_iord_16
    .global cpu_iord_32
    .global cpu_iowr_8
    .global cpu_iowr_16
    .global cpu_iowr_32

    .global mpc8xx_wr_msr
    .global mpc8xx_rd_msr

    .global mpc8xx_wr_dec
    .global mpc8xx_rd_dec

    .global mpc8xx_rd_tbl
    .global mpc8xx_wr_tbl
    .global mpc8xx_rd_tbu
    .global mpc8xx_wr_tbu

    .global mpc8xx_rd_icr

    .global mpc8xx_rd_ictrl
    .global mpc8xx_wr_ictrl

    .global mpc8xx_wr_immr
    .global mpc8xx_rd_immr
    .global mpc8xx_get_immp

    .global mpc8xx_wr_ic_cst
    .global mpc8xx_rd_ic_cst
    .global mpc8xx_wr_ic_adr
    .global mpc8xx_rd_ic_adr
    .global mpc8xx_rd_ic_dat

    .global mpc8xx_wr_dc_cst
    .global mpc8xx_rd_dc_cst
    .global mpc8xx_wr_dc_adr
    .global mpc8xx_rd_dc_adr
    .global mpc8xx_rd_dc_dat


######################################################################

    #
    # Offsets of registers in the REGISTERS data structure.
    # NOTE:  Offsets must match compiler calculated offsets!
    #

    .equ    o_r0,000000
    .equ    o_r1,0x0004
    .equ    o_r2,0x0008
    .equ    o_r3,0x000c
    .equ    o_r4,0x0010
    .equ    o_r5,0x0014
    .equ    o_r6,0x0018
    .equ    o_r7,0x001c
    .equ    o_r8,0x0020
    .equ    o_r9,0x0024
    .equ    o_r10,0x0028
    .equ    o_r11,0x002c
    .equ    o_r12,0x0030
    .equ    o_r13,0x0034
    .equ    o_r14,0x0038
    .equ    o_r15,0x003c
    .equ    o_r16,0x0040
    .equ    o_r17,0x0044
    .equ    o_r18,0x0048
    .equ    o_r19,0x004c
    .equ    o_r20,0x0050
    .equ    o_r21,0x0054
    .equ    o_r22,0x0058
    .equ    o_r23,0x005c
    .equ    o_r24,0x0060
    .equ    o_r25,0x0064
    .equ    o_r26,0x0068
    .equ    o_r27,0x006c
    .equ    o_r28,0x0070
    .equ    o_r29,0x0074
    .equ    o_r30,0x0078
    .equ    o_r31,0x007c
    .equ    o_cr,0x0080
    .equ    o_msr,0x0084
    .equ    o_xer,0x0088
    .equ    o_lr,0x008c
    .equ    o_ctr,0x0090
    .equ    o_dsisr,0x0094
    .equ    o_dar,0x0098
    .equ    o_dec,0x009c
    .equ    o_srr0,0x00a0
    .equ    o_srr1,0x00a4
    .equ    o_tbl,0x00b8
    .equ    o_tbu,0x00bc
    .equ    o_sprg0,0x00a8
    .equ    o_sprg1,0x00ac
    .equ    o_sprg2,0x00b0
    .equ    o_sprg3,0x00b4
    .equ    o_pvr,0x00c0
    .equ    o_8xx_eie,0x00c4
    .equ    o_8xx_eid,0x00c8
    .equ    o_8xx_nri,0x00cc
    .equ    o_8xx_cmpa,0x00d0
    .equ    o_8xx_cmpb,0x00d4
    .equ    o_8xx_cmpc,0x00d8
    .equ    o_8xx_cmpd,0x00dc
    .equ    o_8xx_icr,0x00e0
    .equ    o_8xx_der,0x00e4
    .equ    o_8xx_counta,0x00e8
    .equ    o_8xx_countb,0x00ec
    .equ    o_8xx_cmpe,0x00f0
    .equ    o_8xx_cmpf,0x00f4
    .equ    o_8xx_cmpg,0x00f8
    .equ    o_8xx_cmph,0x00fc
    .equ    o_8xx_lctrl1,0x0100
    .equ    o_8xx_lctrl2,0x0104
    .equ    o_8xx_ictrl,0x0108
    .equ    o_8xx_bar,0x010c
    .equ    o_8xx_dpdr,0x0110
    .equ    o_8xx_dpir,0x0114
    .equ    o_8xx_immr,0x0118
    .equ    o_8xx_ic_cst,0x011c
    .equ    o_8xx_ic_adr,0x0120
    .equ    o_8xx_ic_dat,0x0124
    .equ    o_8xx_dc_cst,0x0128
    .equ    o_8xx_dc_adr,0x012c
    .equ    o_8xx_dc_dat,0x0130
    .equ    o_8xx_mi_ctr,0x0134
    .equ    o_8xx_mi_ap,0x0138
    .equ    o_8xx_mi_epn,0x013c
    .equ    o_8xx_mi_twc,0x0140
    .equ    o_8xx_mi_rpn,0x0144
    .equ    o_8xx_mi_dbcam,0x0148
    .equ    o_8xx_mi_dbram0,0x014c
    .equ    o_8xx_mi_dbram1,0x0150
    .equ    o_8xx_md_ctr,0x0154
    .equ    o_8xx_m_casid,0x0158
    .equ    o_8xx_md_ap,0x015c
    .equ    o_8xx_md_epn,0x0160
    .equ    o_8xx_m_twb,0x0164
    .equ    o_8xx_md_twc,0x0168
    .equ    o_8xx_md_rpn,0x016c
    .equ    o_8xx_m_tw,0x0170
    .equ    o_8xx_md_dbcam,0x0174
    .equ    o_8xx_md_dbram0,0x0178
    .equ    o_8xx_md_dbram1,0x017c


    #
    # PowerPC Special Purpose Register numbers
    #

    .equ    spr_xer,1
    .equ    spr_lr,8
    .equ    spr_ctr,9
    .equ    spr_dsisr,18
    .equ    spr_dar,19
    .equ    spr_dec,22
    .equ    spr_srr0,26
    .equ    spr_srr1,27
    .equ    spr_tbl,268
    .equ    spr_tbu,269
    .equ    spr_sprg0,272
    .equ    spr_sprg1,273
    .equ    spr_sprg2,274
    .equ    spr_sprg3,275
    .equ    spr_pvr,287
    .equ    spr_8xx_eie,80
    .equ    spr_8xx_eid,81
    .equ    spr_8xx_nri,82
    .equ    spr_8xx_cmpa,144
    .equ    spr_8xx_cmpb,145
    .equ    spr_8xx_cmpc,146
    .equ    spr_8xx_cmpd,147
    .equ    spr_8xx_icr,148
    .equ    spr_8xx_der,149
    .equ    spr_8xx_counta,150
    .equ    spr_8xx_countb,151
    .equ    spr_8xx_cmpe,152
    .equ    spr_8xx_cmpf,153
    .equ    spr_8xx_cmpg,154
    .equ    spr_8xx_cmph,155
    .equ    spr_8xx_lctrl1,156
    .equ    spr_8xx_lctrl2,157
    .equ    spr_8xx_ictrl,158
    .equ    spr_8xx_bar,159
    .equ    spr_8xx_dpdr,630
    .equ    spr_8xx_dpir,631
    .equ    spr_8xx_immr,638
    .equ    spr_8xx_ic_cst,560
    .equ    spr_8xx_ic_adr,561
    .equ    spr_8xx_ic_dat,562
    .equ    spr_8xx_dc_cst,568
    .equ    spr_8xx_dc_adr,569
    .equ    spr_8xx_dc_dat,570
    .equ    spr_8xx_mi_ctr,784
    .equ    spr_8xx_mi_ap,786
    .equ    spr_8xx_mi_epn,787
    .equ    spr_8xx_mi_twc,789
    .equ    spr_8xx_mi_rpn,790
    .equ    spr_8xx_mi_dbcam,816
    .equ    spr_8xx_mi_dbram0,817
    .equ    spr_8xx_mi_dbram1,818
    .equ    spr_8xx_md_ctr,792
    .equ    spr_8xx_m_casid,793
    .equ    spr_8xx_md_ap,794
    .equ    spr_8xx_md_epn,795
    .equ    spr_8xx_m_twb,796
    .equ    spr_8xx_md_twc,797
    .equ    spr_8xx_md_rpn,798
    .equ    spr_8xx_m_tw,799
    .equ    spr_8xx_md_dbcam,824
    .equ    spr_8xx_md_dbram0,825
    .equ    spr_8xx_md_dbram1,826


######################################################################

    .text

# This is the entry point upon reset.  The MPC8XX peripherals must be
# initalized properly, beginning with the memory controller, in order for
# the system to start properly.
#
# On the MPC8XX, the part can be configured coming out of power on reset
# by use of a Hard Reset Configuration Word.  This word defines the
# MSR[IP] setting, the boot ROM port size and a few other items.  This
# Config Word is only used if the system asserts RSTCONF_L during
# power-on reset.  If RSTCONF_L is not asserted, then the MPC8XX uses an
# internal default word consisting entirely of zeros.  The Config Word
# looks like (See Chapter 16 of the MPC8XX Spec):
#
# Bit 0:   EARB - External Arbitration
# Bit 1:   IP_ - Initial Interrupt Prefix, IP_ == 0 -> MSR[IP] = 1
# Bit 3:   BDIS - Boot Disable, if 1
# Bit 4,5: Boot Port Size, 00 == 32bit, 01 == 8bit, 10 == 16bit port
# Bit 7,8: Initial Internal Memory Map Reg, 00=0x00000000 01=0x00F00000
#                                           10=0xFF000000 11=0xFFF00000
# Bit 9,10: Debug Pins Config
# Bit 11,12: Debug Port Pins Config
#
# All other bits reserved.

    .equ    IMM_SIZE,0x4000     # 16K Internal Memory Map - DPRAM
    .equ    HR_MSR,0x00001002   # Hard Reset MSR

    .equ    CACHE_DISABLE,0x04000000
    .equ    CACHE_UNLOCK_ALL,0x0A000000
    .equ    CACHE_INVALIDATE,0x0C000000
    .equ    CACHE_ENABLE,0x02000000

asm_startmeup:

    # Step 1)  Disable FPU, Enable Big-Endian, Supervisor Mode,
    # Disable Interrupts, and I- or D- address translation.
    #
    addis   r31,r0,(HR_MSR)@h
    ori     r31,r31,(HR_MSR)@l
    mtmsr   r31
    isync

    # Step 2)  Reset the Instruction cache
    #
    mfspr   r3,spr_8xx_ic_cst           # read to clear bits
    isync
    addis   r3,r0,(CACHE_DISABLE)@h     # force disable
    ori     r3,r3,(CACHE_DISABLE)@l
    bl      mpc8xx_wr_ic_cst
    addis   r3,r0,(CACHE_UNLOCK_ALL)@h  # unlock all
    ori     r3,r3,(CACHE_UNLOCK_ALL)@l
    bl      mpc8xx_wr_ic_cst
    addis   r3,r0,(CACHE_INVALIDATE)@h  # invalidate all
    ori     r3,r3,(CACHE_INVALIDATE)@l
    bl      mpc8xx_wr_ic_cst
#   addis   r3,r0,(CACHE_ENABLE)@h      # icache enabled
#   ori     r3,r3,(CACHE_ENABLE)@l
#   bl      mpc8xx_wr_ic_cst

    # Step 3)  Reset the Data cache
    #
    mfspr   r3,spr_8xx_dc_cst           # read to clear bits
    isync
    addis   r3,r0,(CACHE_DISABLE)@h     # force disable
    ori     r3,r3,(CACHE_DISABLE)@l
    bl      mpc8xx_wr_dc_cst
    addis   r3,r0,(CACHE_UNLOCK_ALL)@h  # unlock all
    ori     r3,r3,(CACHE_UNLOCK_ALL)@l
    bl      mpc8xx_wr_dc_cst
    addis   r3,r0,(CACHE_INVALIDATE)@h  # invalidate all
    ori     r3,r3,(CACHE_INVALIDATE)@l
    bl      mpc8xx_wr_dc_cst

    # Step 4)  Clear out the TLBs
    tlbia
    sync
    isync

    # Step 5)  Determine how we entered Reset processing.

hard_reset:

    # Step 1)  Point R1 to the Dual-Ported RAM to use as stack space
    # until the memory controller is initialized.  Enough space is
    # decremented from top of DPRAM for PPC EABI "back-fill".
    #
    bl      mpc8xx_get_immp         # address of IMM in R3
    addi    r1,r3,IMM_SIZE-20

    bl      mpc8xx_isb              # board location of IMMR[ISB] in r3
    bl      mpc8xx_wr_immr

    addi    r1,r3,IMM_SIZE-20       # re-point r1 into DPRAM

    # Step 2)  Initialize general MPC8XX control modules out of reset.
    #
    bl      mpc8xx_init

soft_reset:

    # Step 3)  Switch to known good debugger stack space.
    #
    addis   r1,r0,(__SP_INIT-20)@h
    ori     r1,r1,(__SP_INIT-20)@l

    # Step 4)  Execute C entry point -- no return
    #
    addis   r3,r0,(main)@h
    ori     r3,r3,(main)@l
    mtspr   spr_lr,r3
    bclrl   20,0            # branch to C main()

######################################################################

#
# When this function is invoked from the exception handler headers
# above, the following is true:
#
# sprg0     == r31
# sprg1     == LR
# LR[16-23] == exception number
#
# This routine then saves the entire context and invokes the C
# exception handler.
#
    .equ    MSR_E_MASK,0x87C0FFFF

asm_exception_body:
    # Point r31 to the user register data structure
    addis   r31,r0,(context)@h
    ori     r31,r31,(context)@l

    # Store all GPRs.
    stw     r0,o_r0(r31)        # store r0
    stw     r1,o_r1(r31)        # store r1
    stw     r2,o_r2(r31)        # store r2
    stw     r3,o_r3(r31)        # store r3
    stw     r4,o_r4(r31)        # store r4
    stw     r5,o_r5(r31)        # store r5
    stw     r6,o_r6(r31)        # store r6
    stw     r7,o_r7(r31)        # store r7
    stw     r8,o_r8(r31)        # store r8
    stw     r9,o_r9(r31)        # store r9
    stw     r10,o_r10(r31)      # store r10
    stw     r11,o_r11(r31)      # store r11
    stw     r12,o_r12(r31)      # store r12
    stw     r13,o_r13(r31)      # store r13
    stw     r14,o_r14(r31)      # store r14
    stw     r15,o_r15(r31)      # store r15
    stw     r16,o_r16(r31)      # store r16
    stw     r17,o_r17(r31)      # store r17
    stw     r18,o_r18(r31)      # store r18
    stw     r19,o_r19(r31)      # store r19
    stw     r20,o_r20(r31)      # store r20
    stw     r21,o_r21(r31)      # store r21
    stw     r22,o_r22(r31)      # store r22
    stw     r23,o_r23(r31)      # store r23
    stw     r24,o_r24(r31)      # store r24
    stw     r25,o_r25(r31)      # store r25
    stw     r26,o_r26(r31)      # store r26
    stw     r27,o_r27(r31)      # store r27
    stw     r28,o_r28(r31)      # store r28
    stw     r29,o_r29(r31)      # store r29
    stw     r30,o_r30(r31)      # store r30

    # Do r31 now.  R31 in sprg0.
    mfspr   r10,spr_sprg0
    stw     r10,o_r31(r31)      # store r31
    sync

    # Zero r0
    addi    r0,0,0

    # Reconstruct MSR
    addis   r10,r0,(MSR_E_MASK)@h
    ori     r10,r10,(MSR_E_MASK)@l
    mfspr   r11,spr_srr1
    and     r11,r10,r11

    addis   r12,r0,(~MSR_E_MASK)@h
    ori     r12,r12,(~MSR_E_MASK)@l
    mfmsr   r13
    isync
    and     r13,r12,r13

    or      r10,r11,r13

    # Save MSR, CR, IP, XER, LR, CTR
    mfcr    r11
    mfspr   r12,spr_srr0
    mfspr   r13,spr_xer
    mfspr   r14,spr_sprg1       # LR from asm_exception_head
    mfspr   r15,spr_ctr
    stw     r10,o_msr(r31)
    stw     r11,o_cr(r31)
    stw     r12,o_srr0(r31)
    stw     r13,o_xer(r31)
    stw     r14,o_lr(r31)
    stw     r15,o_ctr(r31)
    sync

    # Save LR before calling routines (LR contains exception number)
    # (Once LR saved, it is okay to use subroutine calls)
    #
    mfspr   r30,spr_lr
    mtspr   spr_sprg1,r30   # LR from bl in asm_exception_head

    #
    # Change the MSR to suit the needs ot the debugger.
    # No interrupts, tracing, address or data translations.
    #
    .equ    DBUG_MSR,0x00001002
    addis   r30,r0,(DBUG_MSR)@h
    ori     r30,r30,(DBUG_MSR)@l
    mtmsr   r30
    isync

    #
    # Store the Special Purpose Registers
    #

tbloop:
    mftb    r14,269     # TBU
    mftb    r13,268     # TBL
    mftb    r15,269     # TBU
    cmpw    r15,r14
    bne     tbloop
 
    mfspr   r15,spr_pvr
    stw     r13,o_tbl(r31)
    stw     r14,o_tbu(r31)
    stw     r15,o_pvr(r31)
    sync

    mfspr   r13,spr_dsisr
    mfspr   r14,spr_dar
    mfspr   r15,spr_dec
    mfspr   r16,spr_8xx_immr
    stw     r13,o_dsisr(r31)
    stw     r14,o_dar(r31)
    stw     r15,o_dec(r31)
    stw     r16,o_8xx_immr(r31)
    sync

    mfspr   r10,spr_8xx_ic_cst
    mfspr   r11,spr_8xx_ic_adr
    mfspr   r12,spr_8xx_ic_dat
    mfspr   r13,spr_8xx_dc_cst
    mfspr   r14,spr_8xx_dc_adr
    mfspr   r15,spr_8xx_dc_dat
    mfspr   r16,spr_8xx_mi_ctr
    mfspr   r17,spr_8xx_mi_ap
    mfspr   r18,spr_8xx_mi_epn
    mfspr   r19,spr_8xx_mi_twc
    mfspr   r20,spr_8xx_mi_rpn
    mfspr   r21,spr_8xx_mi_dbcam
    mfspr   r22,spr_8xx_mi_dbram0
    mfspr   r23,spr_8xx_mi_dbram1
    stw     r10,o_8xx_ic_cst(r31)
    stw     r11,o_8xx_ic_adr(r31)
    stw     r12,o_8xx_ic_dat(r31)
    stw     r13,o_8xx_dc_cst(r31)
    stw     r14,o_8xx_dc_adr(r31)
    stw     r15,o_8xx_dc_dat(r31)
    stw     r16,o_8xx_mi_ctr(r31)
    stw     r17,o_8xx_mi_ap(r31)
    stw     r18,o_8xx_mi_epn(r31)
    stw     r19,o_8xx_mi_twc(r31)
    stw     r20,o_8xx_mi_rpn(r31)
    stw     r21,o_8xx_mi_dbcam(r31)
    stw     r22,o_8xx_mi_dbram0(r31)
    stw     r23,o_8xx_mi_dbram1(r31)
    sync

    mfspr   r10,spr_8xx_md_ctr
    mfspr   r11,spr_8xx_m_casid
    mfspr   r12,spr_8xx_md_ap
    mfspr   r13,spr_8xx_md_epn
    mfspr   r14,spr_8xx_m_twb