📄 mcf5213_hi.c
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/*
* File: mcf5213_hi.c
* Purpose: Register display/modify routines for MCF5213 modules.
*
* Notes:
*
*/
#include "dbug.h"
#include "cpu.h"
/********************************************************************/
/*
* CPU name string and source code version
*/
#if (defined CPU_MCF5211)
const char CPU_STR[] = "ColdFire MCF5211";
#elif (defined CPU_MCF5212)
const char CPU_STR[] = "ColdFire MCF5212";
#elif (defined CPU_MCF5213)
const char CPU_STR[] = "ColdFire MCF5213";
#endif
const int CPU_VER_MAJOR = 1;
const char CPU_VER_MINOR = 'b';
/********************************************************************/
static const char FORMAT8[] = "%15s : %02X\n";
static const char FORMAT16[] = "%15s : %04X\n";
static const char FORMAT32[] = "%15s : %08X\n";
static const char INVMOD[] = "Error: Invalid Module: %s\n";
#define RD 1 /* read only */
#define WR 2 /* write only */
#define RW 3 /* read/write */
/********************************************************************/
typedef const struct
{
char* rn; /* register name */
uint32 ra; /* register address */
uint8 rs; /* register size */
uint8 rp; /* register privledges (RW) */
} REG;
static const REG SCM[] =
{
{"IPSBAR", (uint32)(&__IPSBAR[0x000000]), 32, RW},
{"RAMBAR", (uint32)(&__IPSBAR[0x000008]), 32, RW},
{"CRSR", (uint32)(&__IPSBAR[0x000010]), 8, RW},
{"CWCR", (uint32)(&__IPSBAR[0x000011]), 8, RW},
{"LPICR", (uint32)(&__IPSBAR[0x000012]), 8, RW},
{"CWSR", (uint32)(&__IPSBAR[0x000013]), 8, RW},
{"PPMRH", (uint32)(&__IPSBAR[0x00000C]), 32, RW},
{"PPMRL", (uint32)(&__IPSBAR[0x000018]), 32, RW}
};
static const REG PMM[] =
{
{"LPICR", (uint32)(&__IPSBAR[0x000012]), 8, RW},
{"LPCR", (uint32)(&__IPSBAR[0x110007]), 8, RW}
};
static const REG DMA[] =
{
{"DMAREQC", (uint32)(&__IPSBAR[0x000014]), 32, RW},
{"SAR0", (uint32)(&__IPSBAR[0x000100]), 32, RW},
{"SAR1", (uint32)(&__IPSBAR[0x000110]), 32, RW},
{"SAR2", (uint32)(&__IPSBAR[0x000120]), 32, RW},
{"SAR3", (uint32)(&__IPSBAR[0x000130]), 32, RW},
{"DAR0", (uint32)(&__IPSBAR[0x000104]), 32, RW},
{"DAR1", (uint32)(&__IPSBAR[0x000114]), 32, RW},
{"DAR2", (uint32)(&__IPSBAR[0x000124]), 32, RW},
{"DAR3", (uint32)(&__IPSBAR[0x000134]), 32, RW},
{"DSR0", (uint32)(&__IPSBAR[0x000108]), 8, RW},
{"DSR1", (uint32)(&__IPSBAR[0x000118]), 8, RW},
{"DSR2", (uint32)(&__IPSBAR[0x000128]), 8, RW},
{"DSR3", (uint32)(&__IPSBAR[0x000138]), 8, RW},
{"BCR0", (uint32)(&__IPSBAR[0x000108]), 32, RW},
{"BCR1", (uint32)(&__IPSBAR[0x000118]), 32, RW},
{"BCR2", (uint32)(&__IPSBAR[0x000128]), 32, RW},
{"BCR3", (uint32)(&__IPSBAR[0x000138]), 32, RW},
{"DCR0", (uint32)(&__IPSBAR[0x00010C]), 32, RW},
{"DCR1", (uint32)(&__IPSBAR[0x00011C]), 32, RW},
{"DCR2", (uint32)(&__IPSBAR[0x00012C]), 32, RW},
{"DCR3", (uint32)(&__IPSBAR[0x00013C]), 32, RW}
};
static const REG UART0[] =
{
{"UMR", (uint32)(&__IPSBAR[0x000200]), 8, RW},
{"USR", (uint32)(&__IPSBAR[0x000204]), 8, RD},
{"UCSR", (uint32)(&__IPSBAR[0x000204]), 8, WR},
{"UCR", (uint32)(&__IPSBAR[0x000208]), 8, WR},
{"URB", (uint32)(&__IPSBAR[0x00020C]), 8, RD},
{"UTB", (uint32)(&__IPSBAR[0x00020C]), 8, WR},
{"UIPCR", (uint32)(&__IPSBAR[0x000210]), 8, RD},
{"UACR", (uint32)(&__IPSBAR[0x000210]), 8, WR},
{"UISR", (uint32)(&__IPSBAR[0x000214]), 8, RD},
{"UIMR", (uint32)(&__IPSBAR[0x000214]), 8, WR},
{"UBG1", (uint32)(&__IPSBAR[0x000218]), 8, WR},
{"UBG2", (uint32)(&__IPSBAR[0x00021C]), 8, WR},
{"UIP", (uint32)(&__IPSBAR[0x000234]), 8, RD},
{"UOP1", (uint32)(&__IPSBAR[0x000238]), 8, WR},
{"UOP0", (uint32)(&__IPSBAR[0x00023C]), 8, WR}
};
static const REG UART1[] =
{
{"UMR", (uint32)(&__IPSBAR[0x000240]), 8, RW},
{"USR", (uint32)(&__IPSBAR[0x000244]), 8, RD},
{"UCSR", (uint32)(&__IPSBAR[0x000244]), 8, WR},
{"UCR", (uint32)(&__IPSBAR[0x000248]), 8, WR},
{"URB", (uint32)(&__IPSBAR[0x00024C]), 8, RD},
{"UTB", (uint32)(&__IPSBAR[0x00024C]), 8, WR},
{"UIPCR", (uint32)(&__IPSBAR[0x000250]), 8, RD},
{"UACR", (uint32)(&__IPSBAR[0x000250]), 8, WR},
{"UISR", (uint32)(&__IPSBAR[0x000254]), 8, RD},
{"UIMR", (uint32)(&__IPSBAR[0x000254]), 8, WR},
{"UBG1", (uint32)(&__IPSBAR[0x000258]), 8, WR},
{"UBG2", (uint32)(&__IPSBAR[0x00025C]), 8, WR},
{"UIP", (uint32)(&__IPSBAR[0x000274]), 8, RD},
{"UOP1", (uint32)(&__IPSBAR[0x000278]), 8, WR},
{"UOP0", (uint32)(&__IPSBAR[0x00027C]), 8, WR}
};
static const REG UART2[] =
{
{"UMR", (uint32)(&__IPSBAR[0x000280]), 8, RW},
{"USR", (uint32)(&__IPSBAR[0x000284]), 8, RD},
{"UCSR", (uint32)(&__IPSBAR[0x000284]), 8, WR},
{"UCR", (uint32)(&__IPSBAR[0x000288]), 8, WR},
{"URB", (uint32)(&__IPSBAR[0x00028C]), 8, RD},
{"UTB", (uint32)(&__IPSBAR[0x00028C]), 8, WR},
{"UIPCR", (uint32)(&__IPSBAR[0x000290]), 8, RD},
{"UACR", (uint32)(&__IPSBAR[0x000290]), 8, WR},
{"UISR", (uint32)(&__IPSBAR[0x000294]), 8, RD},
{"UIMR", (uint32)(&__IPSBAR[0x000294]), 8, WR},
{"UBG1", (uint32)(&__IPSBAR[0x000298]), 8, WR},
{"UBG2", (uint32)(&__IPSBAR[0x00029C]), 8, WR},
{"UIP", (uint32)(&__IPSBAR[0x0002B4]), 8, RD},
{"UOP1", (uint32)(&__IPSBAR[0x0002B8]), 8, WR},
{"UOP0", (uint32)(&__IPSBAR[0x0002BC]), 8, WR}
};
static const REG I2C[] =
{
{"I2AR", (uint32)(&__IPSBAR[0x000300]), 8, RW},
{"I2FDR", (uint32)(&__IPSBAR[0x000304]), 8, RW},
{"I2CR", (uint32)(&__IPSBAR[0x000308]), 8, RW},
{"I2SR", (uint32)(&__IPSBAR[0x00030C]), 8, RW},
{"I2DR", (uint32)(&__IPSBAR[0x000310]), 8, RW},
{"I2ICR", (uint32)(&__IPSBAR[0x000320]), 8, RW}
};
static const REG QSPI[] =
{
{"QMR", (uint32)(&__IPSBAR[0x000340]), 16, RW},
{"QDLYR", (uint32)(&__IPSBAR[0x000344]), 16, RW},
{"QWR", (uint32)(&__IPSBAR[0x000348]), 16, RW},
{"QIR", (uint32)(&__IPSBAR[0x00034C]), 16, RW},
{"QAR", (uint32)(&__IPSBAR[0x000350]), 16, RW},
{"QDR", (uint32)(&__IPSBAR[0x000354]), 16, RW}
};
static const REG DTIM0[] =
{
{"DTMR", (uint32)(&__IPSBAR[0x000400]), 16, RW},
{"DTXMR", (uint32)(&__IPSBAR[0x000402]), 8, RW},
{"DTER", (uint32)(&__IPSBAR[0x000403]), 8, RW},
{"DTRR", (uint32)(&__IPSBAR[0x000404]), 32, RW},
{"DTCR", (uint32)(&__IPSBAR[0x000408]), 32, RW},
{"DTCN", (uint32)(&__IPSBAR[0x00040C]), 32, RW}
};
static const REG DTIM1[] =
{
{"DTMR", (uint32)(&__IPSBAR[0x000440]), 16, RW},
{"DTXMR", (uint32)(&__IPSBAR[0x000442]), 8, RW},
{"DTER", (uint32)(&__IPSBAR[0x000443]), 8, RW},
{"DTRR", (uint32)(&__IPSBAR[0x000444]), 32, RW},
{"DTCR", (uint32)(&__IPSBAR[0x000448]), 32, RW},
{"DTCN", (uint32)(&__IPSBAR[0x00044C]), 32, RW}
};
static const REG DTIM2[] =
{
{"DTMR", (uint32)(&__IPSBAR[0x000480]), 16, RW},
{"DTXMR", (uint32)(&__IPSBAR[0x000482]), 8, RW},
{"DTER", (uint32)(&__IPSBAR[0x000483]), 8, RW},
{"DTRR", (uint32)(&__IPSBAR[0x000484]), 32, RW},
{"DTCR", (uint32)(&__IPSBAR[0x000488]), 32, RW},
{"DTCN", (uint32)(&__IPSBAR[0x00048C]), 32, RW}
};
static const REG DTIM3[] =
{
{"DTMR", (uint32)(&__IPSBAR[0x0004C0]), 16, RW},
{"DTXMR", (uint32)(&__IPSBAR[0x0004C2]), 8, RW},
{"DTER", (uint32)(&__IPSBAR[0x0004C3]), 8, RW},
{"DTRR", (uint32)(&__IPSBAR[0x0004C4]), 32, RW},
{"DTCR", (uint32)(&__IPSBAR[0x0004C8]), 32, RW},
{"DTCN", (uint32)(&__IPSBAR[0x0004CC]), 32, RW}
};
static const REG INTC[] =
{
{"IPRH", (uint32)(&__IPSBAR[0x000C00]), 32, RD},
{"IPRL", (uint32)(&__IPSBAR[0x000C04]), 32, RD},
{"IMRH", (uint32)(&__IPSBAR[0x000C08]), 32, RW},
{"IMRL", (uint32)(&__IPSBAR[0x000C0C]), 32, RW},
{"INTFRCH", (uint32)(&__IPSBAR[0x000C10]), 32, RW},
{"INTFRCL", (uint32)(&__IPSBAR[0x000C14]), 32, RW},
{"IRLR", (uint32)(&__IPSBAR[0x000C18]), 8, RD},
{"IACKLPR", (uint32)(&__IPSBAR[0x000C19]), 8, RD},
{"ICR1", (uint32)(&__IPSBAR[0x000C41]), 8, RD},
{"ICR2", (uint32)(&__IPSBAR[0x000C42]), 8, RD},
{"ICR3", (uint32)(&__IPSBAR[0x000C43]), 8, RD},
{"ICR4", (uint32)(&__IPSBAR[0x000C44]), 8, RD},
{"ICR5", (uint32)(&__IPSBAR[0x000C45]), 8, RD},
{"ICR6", (uint32)(&__IPSBAR[0x000C46]), 8, RD},
{"ICR7", (uint32)(&__IPSBAR[0x000C47]), 8, RD},
{"ICR8", (uint32)(&__IPSBAR[0x000C48]), 8, RW},
{"ICR9", (uint32)(&__IPSBAR[0x000C49]), 8, RW},
{"ICR10", (uint32)(&__IPSBAR[0x000C4A]), 8, RW},
{"ICR11", (uint32)(&__IPSBAR[0x000C4B]), 8, RW},
{"ICR12", (uint32)(&__IPSBAR[0x000C4C]), 8, RW},
{"ICR13", (uint32)(&__IPSBAR[0x000C4D]), 8, RW},
{"ICR14", (uint32)(&__IPSBAR[0x000C4E]), 8, RW},
{"ICR15", (uint32)(&__IPSBAR[0x000C4F]), 8, RW},
{"ICR16", (uint32)(&__IPSBAR[0x000C50]), 8, RW},
{"ICR17", (uint32)(&__IPSBAR[0x000C51]), 8, RW},
{"ICR18", (uint32)(&__IPSBAR[0x000C52]), 8, RW},
{"ICR19", (uint32)(&__IPSBAR[0x000C53]), 8, RW},
{"ICR20", (uint32)(&__IPSBAR[0x000C54]), 8, RW},
{"ICR21", (uint32)(&__IPSBAR[0x000C55]), 8, RW},
{"ICR22", (uint32)(&__IPSBAR[0x000C56]), 8, RW},
{"ICR23", (uint32)(&__IPSBAR[0x000C57]), 8, RW},
{"ICR24", (uint32)(&__IPSBAR[0x000C58]), 8, RW},
{"ICR25", (uint32)(&__IPSBAR[0x000C59]), 8, RW},
{"ICR26", (uint32)(&__IPSBAR[0x000C5A]), 8, RW},
{"ICR27", (uint32)(&__IPSBAR[0x000C5B]), 8, RW},
{"ICR28", (uint32)(&__IPSBAR[0x000C5C]), 8, RW},
{"ICR29", (uint32)(&__IPSBAR[0x000C5D]), 8, RW},
{"ICR30", (uint32)(&__IPSBAR[0x000C5E]), 8, RW},
{"ICR31", (uint32)(&__IPSBAR[0x000C5F]), 8, RW},
{"ICR32", (uint32)(&__IPSBAR[0x000C60]), 8, RW},
{"ICR33", (uint32)(&__IPSBAR[0x000C61]), 8, RW},
{"ICR34", (uint32)(&__IPSBAR[0x000C62]), 8, RW},
{"ICR35", (uint32)(&__IPSBAR[0x000C63]), 8, RW},
{"ICR36", (uint32)(&__IPSBAR[0x000C64]), 8, RW},
{"ICR37", (uint32)(&__IPSBAR[0x000C65]), 8, RW},
{"ICR38", (uint32)(&__IPSBAR[0x000C66]), 8, RW},
{"ICR39", (uint32)(&__IPSBAR[0x000C67]), 8, RW},
{"ICR40", (uint32)(&__IPSBAR[0x000C68]), 8, RW},
{"ICR41", (uint32)(&__IPSBAR[0x000C69]), 8, RW},
{"ICR42", (uint32)(&__IPSBAR[0x000C6A]), 8, RW},
{"ICR43", (uint32)(&__IPSBAR[0x000C6B]), 8, RW},
{"ICR44", (uint32)(&__IPSBAR[0x000C6C]), 8, RW},
{"ICR45", (uint32)(&__IPSBAR[0x000C6D]), 8, RW},
{"ICR46", (uint32)(&__IPSBAR[0x000C6E]), 8, RW},
{"ICR47", (uint32)(&__IPSBAR[0x000C6F]), 8, RW},
{"ICR48", (uint32)(&__IPSBAR[0x000C70]), 8, RW},
{"ICR49", (uint32)(&__IPSBAR[0x000C71]), 8, RW},
{"ICR50", (uint32)(&__IPSBAR[0x000C72]), 8, RW},
{"ICR51", (uint32)(&__IPSBAR[0x000C73]), 8, RW},
{"ICR52", (uint32)(&__IPSBAR[0x000C74]), 8, RW},
{"ICR53", (uint32)(&__IPSBAR[0x000C75]), 8, RW},
{"ICR54", (uint32)(&__IPSBAR[0x000C76]), 8, RW},
{"ICR55", (uint32)(&__IPSBAR[0x000C77]), 8, RW},
{"ICR56", (uint32)(&__IPSBAR[0x000C78]), 8, RW},
{"ICR57", (uint32)(&__IPSBAR[0x000C79]), 8, RW},
{"ICR58", (uint32)(&__IPSBAR[0x000C7A]), 8, RW},
{"ICR59", (uint32)(&__IPSBAR[0x000C7B]), 8, RW},
{"ICR60", (uint32)(&__IPSBAR[0x000C7C]), 8, RW},
{"ICR61", (uint32)(&__IPSBAR[0x000C7D]), 8, RW},
{"ICR62", (uint32)(&__IPSBAR[0x000C7E]), 8, RW},
{"ICR63", (uint32)(&__IPSBAR[0x000C7F]), 8, RW},
{"SWIACK", (uint32)(&__IPSBAR[0x000CE0]), 8, RW},
{"L1IACK", (uint32)(&__IPSBAR[0x000CE4]), 8, RW},
{"L2IACK", (uint32)(&__IPSBAR[0x000CE8]), 8, RW},
{"L3IACK", (uint32)(&__IPSBAR[0x000CEC]), 8, RW},
{"L4IACK", (uint32)(&__IPSBAR[0x000CF0]), 8, RW},
{"L5IACK", (uint32)(&__IPSBAR[0x000CF4]), 8, RW},
{"L6IACK", (uint32)(&__IPSBAR[0x000CF8]), 8, RW},
{"L7IACK", (uint32)(&__IPSBAR[0x000CFC]), 8, RW}
};
static const REG GPIO[] =
{
{"PORTNQ", (uint32)(&__IPSBAR[0x100008]), 8, RW},
{"PORTDD", (uint32)(&__IPSBAR[0x100009]), 8, RW},
{"PORTAN", (uint32)(&__IPSBAR[0x10000A]), 8, RW},
{"PORTAS", (uint32)(&__IPSBAR[0x10000B]), 8, RW},
{"PORTQS", (uint32)(&__IPSBAR[0x10000D]), 8, RW},
{"PORTTA", (uint32)(&__IPSBAR[0x10000E]), 8, RW},
{"PORTTC", (uint32)(&__IPSBAR[0x10000F]), 8, RW},
{"PORTTD", (uint32)(&__IPSBAR[0x100010]), 8, RW},
{"PORTUA", (uint32)(&__IPSBAR[0x100011]), 8, RW},
{"PORTUB", (uint32)(&__IPSBAR[0x100012]), 8, RW},
{"PORTUC", (uint32)(&__IPSBAR[0x100013]), 8, RW},
{"DDRNQ", (uint32)(&__IPSBAR[0x10001C]), 8, RW},
{"DDRDD", (uint32)(&__IPSBAR[0x10001D]), 8, RW},
{"DDRAN", (uint32)(&__IPSBAR[0x10001E]), 8, RW},
{"DDRAS", (uint32)(&__IPSBAR[0x10001F]), 8, RW},
{"DDRQS", (uint32)(&__IPSBAR[0x100021]), 8, RW},
{"DDRTA", (uint32)(&__IPSBAR[0x100022]), 8, RW},
{"DDRTC", (uint32)(&__IPSBAR[0x100023]), 8, RW},
{"DDRTD", (uint32)(&__IPSBAR[0x100024]), 8, RW},
{"DDRUA", (uint32)(&__IPSBAR[0x100025]), 8, RW},
{"DDRUB", (uint32)(&__IPSBAR[0x100026]), 8, RW},
{"DDRUC", (uint32)(&__IPSBAR[0x100027]), 8, RW},
{"SETNQ", (uint32)(&__IPSBAR[0x100030]), 8, RW},
{"SETDD", (uint32)(&__IPSBAR[0x100031]), 8, RW},
{"SETAN", (uint32)(&__IPSBAR[0x100032]), 8, RW},
{"SETAS", (uint32)(&__IPSBAR[0x100033]), 8, RW},
{"SETQS", (uint32)(&__IPSBAR[0x100035]), 8, RW},
{"SETTA", (uint32)(&__IPSBAR[0x100036]), 8, RW},
{"SETTC", (uint32)(&__IPSBAR[0x100037]), 8, RW},
{"SETTD", (uint32)(&__IPSBAR[0x100038]), 8, RW},
{"SETUA", (uint32)(&__IPSBAR[0x100039]), 8, RW},
{"SETUB", (uint32)(&__IPSBAR[0x10003A]), 8, RW},
{"SETUC", (uint32)(&__IPSBAR[0x10003B]), 8, RW},
{"CLRNQ", (uint32)(&__IPSBAR[0x100044]), 8, RW},
{"CLRDD", (uint32)(&__IPSBAR[0x100045]), 8, RW},
{"CLRAN", (uint32)(&__IPSBAR[0x100046]), 8, RW},
{"CLRAS", (uint32)(&__IPSBAR[0x100047]), 8, RW},
{"CLRQS", (uint32)(&__IPSBAR[0x100049]), 8, RW},
{"CLRTA", (uint32)(&__IPSBAR[0x10004A]), 8, RW},
{"CLRTC", (uint32)(&__IPSBAR[0x10004B]), 8, RW},
{"CLRTD", (uint32)(&__IPSBAR[0x10004C]), 8, RW},
{"CLRUA", (uint32)(&__IPSBAR[0x10004D]), 8, RW},
{"CLRUB", (uint32)(&__IPSBAR[0x10004E]), 8, RW},
{"CLRUC", (uint32)(&__IPSBAR[0x10004F]), 8, RW},
{"PNQPAR", (uint32)(&__IPSBAR[0x100050]), 8, RW},
{"PDDPAR", (uint32)(&__IPSBAR[0x100051]), 8, RW},
{"PANPAR", (uint32)(&__IPSBAR[0x100052]), 8, RW},
{"PASPAR", (uint32)(&__IPSBAR[0x100053]), 8, RW},
{"PQSPAR", (uint32)(&__IPSBAR[0x100054]), 16, RW},
{"PTAPAR", (uint32)(&__IPSBAR[0x100056]), 8, RW},
{"PTCPAR", (uint32)(&__IPSBAR[0x100057]), 8, RW},
{"PTDPAR", (uint32)(&__IPSBAR[0x100058]), 8, RW},
{"PUAPAR", (uint32)(&__IPSBAR[0x100059]), 8, RW},
{"PUBPAR", (uint32)(&__IPSBAR[0x10005A]), 8, RW},
{"PUCPAR", (uint32)(&__IPSBAR[0x10005B]), 8, RW},
{"PSRR", (uint32)(&__IPSBAR[0x100078]), 32, RW},
{"PDSR", (uint32)(&__IPSBAR[0x10007C]), 32, RW}
};
static const REG CIM[] =
{
{"RCR", (uint32)(&__IPSBAR[0x110000]), 8, RW},
{"RSR", (uint32)(&__IPSBAR[0x110001]), 8, RW},
{"CCR", (uint32)(&__IPSBAR[0x110004]), 16, RW},
{"LPCR", (uint32)(&__IPSBAR[0x110007]), 8, RW},
{"RCON", (uint32)(&__IPSBAR[0x110008]), 16, RW},
{"CIR", (uint32)(&__IPSBAR[0x11000A]), 16, RW}
};
static const REG CLOCK[] =
{
{"SYNCR", (uint32)(&__IPSBAR[0x120000]), 16, RW},
{"SYNSR", (uint32)(&__IPSBAR[0x120002]), 8, RW},
{"LPCR", (uint32)(&__IPSBAR[0x120007]), 8, RW}
};
static const REG EPORT[] =
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