mcf548x_lo.s

motorola 针对coldfire 5275 评估板的Dbug bootloader源程序

/*
 * File:    mcf548x_lo.s
 * Purpose: Lowest level routines for mcf548x.
 *
 * Notes:   
 *
 */

#ifdef _UNDERSCORE_
#define __MBAR              ___MBAR
#define __CORE_SRAM0        ___CORE_SRAM0
#define __CORE_SRAM1        ___CORE_SRAM1
#define __CORE_SRAM0_SIZE   ___CORE_SRAM0_SIZE
#define __CORE_SRAM1_SIZE   ___CORE_SRAM1_SIZE
#define __SP_INIT           ___SP_INIT
#define mcf548x_init        _mcf548x_init
#define main                _main
#define asm_set_ipl         _asm_set_ipl
#endif
 
    .extern __MBAR
    .extern __CORE_SRAM0
    .extern __CORE_SRAM1
    .extern __CORE_SRAM0_SIZE
    .extern __CORE_SRAM1_SIZE
    .extern __SP_INIT
    .extern mcf548x_init
    .extern main
    .extern asm_set_ipl
 
    .global asm_startmeup
    .global _asm_startmeup
    .global cpu_cache_flush
    .global _cpu_cache_flush
    .global cpu_cache_disable
    .global _cpu_cache_disable

    .text

/********************************************************************
 * This is the main entry point upon hard reset.
 */
asm_startmeup:
_asm_startmeup:
    
    /* Initialize MBAR */
    move.l  #__MBAR,d0
    movec   d0,MBAR
    
    /* Initialize RAMBAR0 - locate it on the data bus */
    move.l  #__CORE_SRAM0,d0
    add.l   #0x21,d0
    movec   d0,RAMBAR0

    /* Initialize RAMBAR1 - locate it on the data bus */
    move.l  #__CORE_SRAM1,d0
    add.l   #0x21,d0
    movec   d0,RAMBAR1

    /* Point Stack Pointer into Core SRAM temporarily */
    move.l  #__CORE_SRAM1,d0
    add.l   #__CORE_SRAM1_SIZE,d0
    move.l  d0,SP

    /* Invalidate the data, instruction, and branch caches */
    /* Turn on the branch cache */
    move.l  #0x010C0100,d0
    movec   d0,cacr

    /* Initialize mcf548x periphs, etc */
    jsr     mcf548x_init

    /* Relocate Stack Pointer */ 
    move.l  #__SP_INIT,SP

    /* Jump to the main process */
    jsr     main
    
    bra     .
    nop
    nop
    halt

/********************************************************************
 *  Routine to cleanly flush the cache, pushing all lines and 
 *  invalidating them.  This must be done to change the cache when 
 *  we have been operating in copyback mode (i.e. writes to a copyback 
 *  region are probably resident in the cache and not in the main store).
 */
_cpu_cache_flush:
cpu_cache_flush:
    nop                 /* synchronize - flush store buffer */
    moveq.l #0,d0       /* init way counter */
    moveq.l #0,d1       /* init set counter */
    move.l  d0,a0       /* init An */

flushloop:

    .word   0xF4E8      /* cpushl bc,(a0) -- push cache line */

    add.l   #0x0010,a0  /* increment setindex by 1 */
    addq.l  #1,d1       /* increment set counter */
    cmpi.l  #512,d1     /* are sets for this line done? */
    bne     flushloop

    moveq.l #0,d1       /* set counter to zero again */
    addq.l  #1,d0       /* increment to next line */
    move.l  d0,a0       /* set 0, line d0 into a0 as per cpushl */
    cmpi.l  #4,d0
    bne     flushloop

    rts

/********************************************************************
 *  Routine to disable the cache completely
 */
_cpu_cache_disable:
cpu_cache_disable:

    move.l  #0x7,-(SP)      /* Disable interrupts (set IPL = 7) */      
    jsr     asm_set_ipl
    lea.l   4(SP),SP
    move.l  d0,d1

    jsr     _cpu_cache_flush    /* flush the cache completely */    

    clr.l   d0
    movec   d0,ACR0         /* ACR0 off */
    movec   d0,ACR1         /* ACR1 off */
    movec   d0,ACR2         /* ACR2 off */
    movec   d0,ACR3         /* ACR3 off */

    move.l  #0x01000100,d0  /* Invalidate and disable cache */
    movec   d0,CACR
    
    move.l  d1,-(SP)        /* Restore interrupt level */       
    jsr     asm_set_ipl
    lea.l   4(SP),SP

    rts

/********************************************************************/
    .end