📄 mcf5xxx_hi.c
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int i, size = SIZE_16;
for (i = 0; arg[i] != '\0'; i++)
{
if (arg[i] == '.')
{
switch (arg[i+1])
{
case 'b':
case 'B':
size = SIZE_8;
break;
case 'w':
case 'W':
size = SIZE_16;
break;
case 'l':
case 'L':
size = SIZE_32;
break;
default:
size = SIZE_16;
break;
}
break;
}
}
return size;
}
/********************************************************************/
int
cpu_valid_insn_addr (ADDRESS address)
{
/* ColdFire requires instructions be on 16-bit boundary */
return !(address & 0x00000001);
}
/********************************************************************/
void
cpu_switch_context (int trace)
{
/*
* If 'trace' is TRUE, then we are performing a single
* instruction trace, thus, do not insert breakponts.
* Otherwise, install breakpoints and run normally.
*/
if (trace)
{
context.sr |= MCF5XXX_SR_T;
}
else
{
if (breakpoint_install(context.pc))
{
/*
* The PC is at a breakpoint already. Trace thru
* this breakpoint rather than actually breaking.
*/
trace_thru = context.pc;
context.sr |= MCF5XXX_SR_T;
}
}
asm_switch_context(&context);
}
/********************************************************************/
void
cpu_write_data (ADDRESS address, int size, uint32 data)
{
switch (size)
{
case SIZE_8:
*((uint8 *)address) = (uint8)data;
break;
case SIZE_16:
*((uint16 *)address) = (uint16)data;
break;
case SIZE_32:
*((uint32 *)address) = (uint32)data;
break;
default:
break;
}
}
/********************************************************************/
uint32
cpu_read_data (ADDRESS address, int size)
{
switch (size)
{
case SIZE_8:
return *((uint8 *)address);
case SIZE_16:
return *((uint16 *)address);
case SIZE_32:
return *((uint32 *)address);
default:
return 0;
}
}
/********************************************************************/
ADDRESS
cpu_align_address (ADDRESS address, int size)
{
switch (size)
{
case SIZE_16:
return (address & ~0x00000001);
case SIZE_32:
return (address & ~0x00000003);
case SIZE_8:
default:
return (address);
}
}
/********************************************************************/
ADDRESS
cpu_stack_frame (ADDRESS fp, ADDRESS *retpc)
{
/*
* ColdFire/M68K JSR w/LINK and UNLK w/RTS
*/
if (retpc == NULL)
{
return context.a6;
}
else
{
*retpc = *(ADDRESS *)(fp + 4);
return *(ADDRESS *)fp;
}
}
/********************************************************************/
int
cpu_handler (void *framep)
{
/*
* This is the exception handler for all defined exceptions. Most
* exceptions do nothing, but some of the more important ones are
* handled to some extent.
*/
int ispdelta;
int cpu_handler_flag;
int user_brkpnt, user_triggered;
/*
* Default action for most exceptions is to break to monitor.
*/
cpu_handler_flag = EXEC_DBUG;
/*
* Update context.sp to point to prior to stack frame.
*/
switch (MCF5XXX_RD_SF_FORMAT(framep))
{
case 4:
ispdelta = 8;
break;
case 5:
ispdelta = 9;
break;
case 6:
ispdelta = 10;
break;
case 7:
ispdelta = 11;
break;
default:
printf("\nIllegal stack type!\n");
ispdelta = 0;
break;
}
context.a7 += ispdelta;
user_brkpnt = breakpoint_deinstall(context.pc, &user_triggered);
switch (MCF5XXX_RD_SF_VECTOR(framep))
{
case 2:
printf("Access Error: ");
dump_fs(framep);
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
case 3:
printf("Address Error: ");
dump_fs(framep);
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
case 4:
if (!user_brkpnt)
{
printf("Illegal instruction at %#08X\n",context.pc);
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
}
if (cpu_step_over == context.pc)
{
/* clean up is at end of handler */
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
}
if (user_triggered)
{
printf("Breakpoint encountered at %#08X\n",context.pc);
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
}
/* else reinstall breakpoints and continue */
/* execution of the task...we will return */
/* to task from here, not write out regs and RTE */
if (breakpoint_install(context.pc))
{
/* about to execute at a breakpoint */
/* trace thru this breakpoint rather breaking */
trace_thru = context.pc;
/* turn tracing on */
MCF5XXX_SF_SR(framep) |= MCF5XXX_SR_T;
/* readjust stack pointer for RTE */
context.a7 -= ispdelta;
cpu_handler_flag = EXEC_RTE;
}
break;
case 8:
printf("Privilege violation\n");
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
case 9:
if (trace_thru)
{
/* place breakpoint at trace_thru */
cpu_write_data(trace_thru, SIZE_16, ILLEGAL);
/* turn off tracing */
context.sr &= ~MCF5XXX_SR_T;
/* nullify trace_thru and continue execution */
trace_thru = 0;
cpu_handler_flag = EXEC_RTE;
/* adjust user stack back so RTE frame correct */
context.a7 -= ispdelta;
/* since not recreating a new stack frame, must */
/* turn off trace bit in SR already on stack. */
MCF5XXX_SF_SR(framep) &= ~MCF5XXX_SR_T;
break;
}
/* each time through, decrement cpu_trace_count */
if (--cpu_trace_count > 0)
{
context.a7 -= ispdelta;
cpu_handler_flag = EXEC_RTE;
}
else
{
/* since not recreating a new stack frame, must */
/* turn off trace bit in SR already on stack. */
MCF5XXX_SF_SR(framep) &= ~MCF5XXX_SR_T;
/* turn off tracing */
context.sr &= ~MCF5XXX_SR_T;
cpu_handler_flag = EXEC_DBUG;
cpu_trace_count = 0;
}
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
case 10:
printf("Unimplemented A-Line Instruction\n");
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
case 11:
printf("Unimplemented F-Line Instruction\n");
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
case 12:
printf("Debug Interrupt\n");
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
case 14:
printf("Format Error\n");
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
case 15:
printf("Unitialized Interrupt\n");
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
case 24:
printf("Spurious Interrupt\n");
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
case 25:
case 26:
case 27:
case 28:
case 29:
case 30:
case 31:
printf("Autovector interrupt level %d\n",
MCF5XXX_RD_SF_VECTOR(framep) - 24);
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
case 32:
case 33:
case 34:
case 35:
case 36:
case 37:
case 38:
case 39:
case 40:
case 41:
case 42:
case 43:
case 44:
case 45:
case 46:
case 47:
printf("TRAP #%d\n", MCF5XXX_RD_SF_VECTOR(framep) - 32);
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
case 5:
case 6:
case 7:
case 13:
case 16:
case 17:
case 18:
case 19:
case 20:
case 21:
case 22:
case 23:
case 48:
case 49:
case 50:
case 51:
case 52:
case 53:
case 54:
case 55:
case 56:
case 57:
case 58:
case 59:
case 60:
case 61:
case 62:
case 63:
printf("Reserved: #%d\n",
MCF5XXX_RD_SF_VECTOR(framep));
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
default:
/* Handle User Defined interrupts 64-255 */
cpu_handle_interrupt(MCF5XXX_RD_SF_VECTOR(framep));
cpu_reg_display(NULL);
cpu_disasm(context.pc,TRUE);
break;
}
if ((cpu_handler_flag == EXEC_DBUG) && cpu_step_over)
{
breakpoint_remove(cpu_step_over);
cpu_step_over = 0;
}
return cpu_handler_flag;
}
/********************************************************************/
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