mcf5407_lo.s

motorola 针对coldfire 5275 评估板的Dbug bootloader源程序

/*
 * File:    mcf5407_lo.s
 * Purpose: Lowest level routines for mcf5407.
 *
 * Notes:   
 *
 */

#ifdef _UNDERSCORE_
#define mcf5407_mbar     _mcf5407_mbar
#define mcf5407_rambar0  _mcf5407_rambar0
#define mcf5407_rambar1  _mcf5407_rambar1
#define mcf5407_init     _mcf5407_init
#define main             _main
#endif
 
    .extern ___SP_INIT
    .extern VECTOR_TABLE
    .extern mcf5407_mbar
    .extern mcf5407_rambar0
    .extern mcf5407_rambar1
    .extern mcf5407_init
    .extern main
 
    .global asm_startmeup
    .global _asm_startmeup

    .global asm_execute_user_flash
    .global _asm_execute_user_flash
 
    .global cpu_cache_flush
    .global _cpu_cache_flush

    .global _cpu_cache_disable
    .global cpu_cache_disable

    .equ    SRAMsize,2048-0x10 

    .text

/*
 * This is the main entry point upon hard reset.
 */
asm_startmeup:
_asm_startmeup:

    move.w      #0x2700,SR
    move.l      #VECTOR_TABLE,d0
    movec       d0,VBR

    /* Invalidate the cache and disable it */
    move.l  #0x01000000,d0
    .long   0x4e7b0002      /* movec d0,cacr */

    /* Disable ACRs */
    moveq.l #0,d0
    .long   0x4e7b0004      /* movec d0,ACR0 */
    .long   0x4e7b0005      /* movec d0,ACR1 */
    .long   0x4e7b0006      /* movec d0,ACR2 */
    .long   0x4e7b0007      /* movec d0,ACR3 */    

    /* Initialize HW Return Stack */
    move.l  #0xC0000,d0
    movec.l d0,CACR
    bsr.w   .+4
    bsr.w   .+4
    bsr.w   .+4
    bsr.w   .+4
    lea     16(a7),a7
    
    /* Initialize RAMBAR0 */
    move.l  #0xE0000001,d0  /* locate SRAM, validate it! */
    .long   0x4e7b0C04      /* movec d0,RAMBAR0 */


    nop
    nop

    /*
     * Point SP into SRAM (temporarily).  SRAM is used as stack space
     * while initializing the mcf5407 periphs and memory controller.
     */
    move.l  #0xE0000000+SRAMsize,SP

    /* Obtain pointer to where MBAR is to be mapped */
    jsr     mcf5407_mbar
    move.l  d0,d6

    /* Obtain pointer to where RAMBAR0 is to be mapped */
    jsr     mcf5407_rambar0

    /* Adjust SP to (soon to be valid) SRAM */
    move.l  d0,a0
    lea     SRAMsize(a0),SP

    /* Map RAMBAR0 and MBAR */
    addq.l  #1,d0           /* Set Valid bit */
    .long   0x4e7b0C04      /* movec d0,RAMBAR0 */

    move.l  d6,d0
    addq.l  #1,d0           /* Set Valid bit */
    .long   0x4e7b0C0F      /* movec d0,MBAR */

    /* Obtain pointer to where RAMBAR1 is to be mapped */
    jsr     mcf5407_rambar1

    /* Map RAMBAR1 */
    addq.l  #1,d0           /* Set Valid bit */
    .long   0x4e7b0C05      /* movec d0,RAMBAR1 */


    /* Initialize mcf5407 periphs, etc */
    move.l  d6,-(sp)        /* pointer to internal resources */
    jsr     mcf5407_init
    lea     4(sp),sp

    /*
     * Point SP to DRAM.  DRAM may only be visible once CS0 
     * de-activated as global chipselect.
     */
    move.l  #___SP_INIT,sp

    nop
    nop

    jmp     main

/*******************************************************************/
_asm_execute_user_flash:
asm_execute_user_flash:
        move.l  8(sp),a0    /* get new PC */
        move.l  4(sp),a7    /* get new SP */
        clr.l   d0          
        movec   d0,VBR      /* reset VBR to reset value */
        jmp (a0)            /* execute at new PC */

/********************************************************************
 *  Routine to cleanly flush the cache, pushing all lines and 
 *  invalidating them.  This must be done to change the cache when 
 *  we have been operating in copyback mode (i.e. writes to a copyback 
 *  region are probably resident in the cache and not in the main store).
 */
_cpu_cache_flush:
cpu_cache_flush:
    nop                 /* synchronize - flush store buffer */

    moveq.l #0,d0       /* init line counter */
    moveq.l #0,d1       /* init set counter */
    move.l  d0,a0       /* init An */

flushloop:

    cpushl  (a0)        /* push cache line a0 - GNU Compiler */
/*  cpushl  bc,(a0) */  /* push cache line a0 - Diab Compiler */

    add.l   #0x0010,a0  /* increment setindex by 1 */
    addq.l  #1,d1       /* increment set counter */
    cmpi.l  #128,d1     /* are sets for this line done? */
    bne     flushloop

    moveq.l #0,d1       /* set counter to zero again */
    addq.l  #1,d0       /* increment to next line */
    move.l  d0,a0       /* set 0, line d0 into a0 as per cpushl */
    cmpi.l  #4,d0
    bne     flushloop

    rts

/********************************************************************
 *  Routine to disable to cache completely
 *  THIS ROUTINE DISABLES IRQ's -- be warned
 */
_cpu_cache_disable:
cpu_cache_disable:
    nop
    move.w  #0x2700,SR      /* mask off IRQ's */
    jsr     _cpu_cache_flush    /* flush the cache completely */    
    clr.l   d0
    movec   d0,ACR0         /* ACR0 off */
    movec   d0,ACR1         /* ACR1 off */
    movec   d0,ACR2         /* ACR2 off */
    movec   d0,ACR3         /* ACR3 off */

    move.l  #0x01000000,d0  /* Invalidate and disable cache */
    movec   d0,CACR
    rts

    .end