📄 mcf5249_lo.s
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/*
* File: mcf5249_lo.s
* Purpose: Lowest level routines for mcf5249.
*
* Notes: This file assembles with both Diab and GNU tools
*
*/
#ifdef _UNDERSCORE_
#define mcf5249_init _mcf5249_init
#define main _main
#endif
.extern ___MBAR;
.extern ___MBAR2;
.extern ___SRAM0;
.extern ___SRAM1;
.extern ___SP_INIT
.extern mcf5249_init
.extern main
.global asm_startmeup
.global _asm_startmeup
.global cpu_cache_flush
.global _cpu_cache_flush
.equ SRAMsize,0x08000
.text
/********************************************************************/
/*
* This is the main entry point upon hard reset.
*/
asm_startmeup:
_asm_startmeup:
/* Initialize RAMBARs: locate SRAM and validate it */
move.l #(___SRAM0 + 0x21),d0
movec d0,RAMBAR0
move.l #(___SRAM1 + 0x21),d0
movec d0,RAMBAR1
/* Point Stack Pointer into SRAM temporarily */
move.l #(___SRAM0 + SRAMsize),sp
/* Initalize MBARs */
move.l #(___MBAR + 1),d0
movec d0,MBAR
move.l #(___MBAR2 + 1),d0
.long 0x4e7b0C0E /* movec d0,MBAR2 */
/* Initialize mcf5249 periphs, etc */
jsr mcf5249_init
/* Relocate Stack Pointer */
move.l #___SP_INIT,sp
/* Jump to the main process */
jmp main
bra .
nop
nop
halt
/********************************************************************/
/*
* The MCF5249 has Icache only
*/
cpu_cache_flush:
_cpu_cache_flush:
nop /* sync */
move.l #0x01000000,d0 /* Invalidate the I-Cache */
movec d0,cacr
rts
/********************************************************************/
.end
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