📄 mcf5208_hi.c
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printf(INVREG,reg);
}
/********************************************************************/
static void
irmd_eport (char *reg, int regread, uint32 value)
{
IRMD(EPORT, EPPAR, 16);
IRMD(EPORT, EPDDR, 8);
IRMD(EPORT, EPIER, 8);
IRMD(EPORT, EPDR, 8);
IRMD(EPORT, EPPDR, 8);
IRMD(EPORT, EPFR, 8);
if (!display_all)
printf(INVREG,reg);
}
/********************************************************************/
static void
irmd_wtm (char *reg, int regread, uint32 value)
{
IRMD(WTM, WCR, 16);
IRMD(WTM, WMR, 16);
IRMD(WTM, WCNTR, 16);
IRMD(WTM, WSR, 16);
if (!display_all)
printf(INVREG,reg);
}
/********************************************************************/
static void
irmd_pll (char *reg, int regread, uint32 value)
{
IRMD(PLL, PODR, 8);
IRMD(PLL, PLLCR, 8);
IRMD(PLL, PMDR, 8);
IRMD(PLL, PFDR, 8);
if (!display_all)
printf(INVREG,reg);
}
/********************************************************************/
static void
irmd_gpio (char *reg, int regread, uint32 value)
{
IRMD(GPIO, PODR_BUSCTL, 8);
IRMD(GPIO, PODR_BE, 8);
IRMD(GPIO, PODR_CS, 8);
IRMD(GPIO, PODR_FECI2C, 8);
IRMD(GPIO, PODR_QSPI, 8);
IRMD(GPIO, PODR_TIMER, 8);
IRMD(GPIO, PODR_UART, 8);
IRMD(GPIO, PODR_FECH, 8);
IRMD(GPIO, PODR_FECL, 8);
IRMD(GPIO, PDDR_BUSCTL, 8);
IRMD(GPIO, PDDR_BE, 8);
IRMD(GPIO, PDDR_CS, 8);
IRMD(GPIO, PDDR_FECI2C, 8);
IRMD(GPIO, PDDR_QSPI, 8);
IRMD(GPIO, PDDR_TIMER, 8);
IRMD(GPIO, PDDR_UART, 8);
IRMD(GPIO, PDDR_FECH, 8);
IRMD(GPIO, PDDR_FECL, 8);
IRMD(GPIO, PPDSDR_BUSCTL, 8);
IRMD(GPIO, PPDSDR_BE, 8);
IRMD(GPIO, PPDSDR_CS, 8);
IRMD(GPIO, PPDSDR_FECI2C, 8);
IRMD(GPIO, PPDSDR_QSPI, 8);
IRMD(GPIO, PPDSDR_TIMER, 8);
IRMD(GPIO, PPDSDR_UART, 8);
IRMD(GPIO, PPDSDR_FECH, 8);
IRMD(GPIO, PPDSDR_FECL, 8);
IRMD(GPIO, PCLRR_BUSCTL, 8);
IRMD(GPIO, PCLRR_BE, 8);
IRMD(GPIO, PCLRR_CS, 8);
IRMD(GPIO, PCLRR_FECI2C, 8);
IRMD(GPIO, PCLRR_QSPI, 8);
IRMD(GPIO, PCLRR_TIMER, 8);
IRMD(GPIO, PCLRR_UART, 8);
IRMD(GPIO, PCLRR_FECH, 8);
IRMD(GPIO, PCLRR_FECL, 8);
IRMD(GPIO, PAR_BUSCTL, 8);
IRMD(GPIO, PAR_BE, 8);
IRMD(GPIO, PAR_CS, 8);
IRMD(GPIO, PAR_FECI2C, 8);
IRMD(GPIO, PAR_QSPI, 8);
IRMD(GPIO, PAR_TIMER, 8);
IRMD(GPIO, PAR_UART, 8);
IRMD(GPIO, PAR_FEC, 8);
IRMD(GPIO, PAR_IRQ, 8);
IRMD(GPIO, MSCR_FLEXBUS, 8);
IRMD(GPIO, MSCR_SDRAM, 8);
IRMD(GPIO, DSCR_I2C, 8);
IRMD(GPIO, DSCR_MISC, 8);
IRMD(GPIO, DSCR_FEC, 8);
IRMD(GPIO, DSCR_UART, 8);
IRMD(GPIO, DSCR_QSPI, 8);
if (!display_all)
printf(INVREG,reg);
}
/********************************************************************/
static void
irmd_sdramc (char *reg, int regread, uint32 value)
{
IRMD(SDRAMC, SDMR, 32);
IRMD(SDRAMC, SDCR, 32);
IRMD(SDRAMC, SDCFG1, 32);
IRMD(SDRAMC, SDCFG2, 32);
IRMD(SDRAMC, SDCS0, 32);
IRMD(SDRAMC, SDCS1, 32);
if (!display_all)
printf(INVREG,reg);
}
/********************************************************************/
static void
irmd_xbs (char *reg, int regread, uint32 value)
{
IRMD(XBS, PRS1, 32);
IRMD(XBS, PRS2, 32);
IRMD(XBS, PRS3, 32);
IRMD(XBS, PRS4, 32);
IRMD(XBS, PRS5, 32);
IRMD(XBS, PRS6, 32);
IRMD(XBS, PRS7, 32);
IRMD(XBS, CRS1, 32);
IRMD(XBS, CRS2, 32);
IRMD(XBS, CRS3, 32);
IRMD(XBS, CRS4, 32);
IRMD(XBS, CRS5, 32);
IRMD(XBS, CRS6, 32);
IRMD(XBS, CRS7, 32);
if (!display_all)
printf(INVREG,reg);
}
/********************************************************************/
static void
irmd_pmm (char *reg, int regread, uint32 value)
{
IRMD(PMM, WCR, 8);
IRMD(PMM, PPMSR0, 8);
IRMD(PMM, PPMSR1, 8);
IRMD(PMM, PPMCR0, 8);
IRMD(PMM, PPMCR1, 8);
IRMD(PMM, PPMHR0, 32);
IRMD(PMM, PPMHR1, 32);
IRMD(PMM, LPCR, 8);
IRMD(PMM, MISCCR, 16);
if (!display_all)
printf(INVREG,reg);
}
/********************************************************************/
static void
irmd_rcm (char *reg, int regread, uint32 value)
{
IRMD(RCM, RCR, 8);
IRMD(RCM, RSR, 8);
if (!display_all)
printf(INVREG,reg);
}
/********************************************************************/
static void
irmd_ccm (char *reg, int regread, uint32 value)
{
IRMD(CCM, CCR, 16);
IRMD(CCM, RCON, 16);
IRMD(CCM, CIR, 16);
if (!display_all)
printf(INVREG,reg);
}
/********************************************************************/
static const struct module_t
{
char *module;
void (*func)(char *, int, uint32);
} MODULE[] =
{
{"SCM", irmd_scm},
{"XBS", irmd_xbs},
{"FBCS", irmd_fbcs},
{"FEC", irmd_fec},
{"PMM", irmd_pmm},
{"EDMA", irmd_edma},
{"EDMA_TCD0",irmd_edma_tcd0},
{"EDMA_TCD1",irmd_edma_tcd1},
{"EDMA_TCD2",irmd_edma_tcd2},
{"EDMA_TCD3",irmd_edma_tcd3},
{"EDMA_TCD4",irmd_edma_tcd4},
{"EDMA_TCD5",irmd_edma_tcd5},
{"EDMA_TCD6",irmd_edma_tcd6},
{"EDMA_TCD7",irmd_edma_tcd7},
{"EDMA_TCD8",irmd_edma_tcd8},
{"EDMA_TCD9",irmd_edma_tcd9},
{"EDMA_TCD10",irmd_edma_tcd10},
{"EDMA_TCD11",irmd_edma_tcd11},
{"EDMA_TCD12",irmd_edma_tcd12},
{"EDMA_TCD13",irmd_edma_tcd13},
{"EDMA_TCD14",irmd_edma_tcd14},
{"EDMA_TCD15",irmd_edma_tcd15},
{"INTC", irmd_intc},
{"INTC_IACK", irmd_intc_iack},
{"I2C", irmd_i2c},
{"QSPI", irmd_qspi},
{"UART0", irmd_uart0},
{"UART1", irmd_uart1},
{"UART2", irmd_uart2},
{"TIMER0", irmd_dma_timer0},
{"TIMER1", irmd_dma_timer1},
{"TIMER2", irmd_dma_timer2},
{"TIMER3", irmd_dma_timer3},
{"PIT0", irmd_pit0},
{"PIT1", irmd_pit1},
{"EPORT", irmd_eport},
{"WTM", irmd_wtm},
{"RCM", irmd_rcm},
{"CCM", irmd_ccm},
{"PLL", irmd_pll},
{"GPIO", irmd_gpio},
{"SDRAMC", irmd_sdramc}
};
#define MODULE_SIZE (int)(sizeof(MODULE)/sizeof(struct module_t))
/********************************************************************/
void
mcf5208_irmd (int argc, char **argv)
{
uint32 value;
char *rstr;
char mstr[20];
int mi, success;
display_all = FALSE;
displayed = 0;
if (argc == 1)
{
for (mi = 0; mi < MODULE_SIZE; ++mi)
{
if (!(mi % 6))
printf("\n");
printf("%-11s ",MODULE[mi].module);
}
printf("\n\n");
return;
}
/*
* Pick out module name and Point to register name
*/
mi = 0;
rstr = argv[1];
while (*rstr != '.')
{
mstr[mi++] = *rstr;
if (*++rstr == '\0')
{
rstr = NULL;
break;
}
}
mstr[mi] = '\0';
if (rstr != NULL)
{
if (*rstr == '.')
++rstr;
}
/*
* Get the new value
*/
if (argc == 3)
{
if (rstr == NULL)
{
printf("Error: Invalid Register: %s\n",argv[1]);
return;
}
value = get_value(argv[2],&success,16);
if (success == 0)
{
printf(INVALUE,argv[2]);
return;
}
}
else
value = 0;
/*
* Determine which module
*/
for (mi = 0; mi < MODULE_SIZE; ++mi)
{
if (strcasecmp(MODULE[mi].module,mstr) == 0)
{
if (argc == 3) /* modify operation */
{
MODULE[mi].func(rstr, REGWRITE, value);
}
else
{
/* display operation */
if (rstr == NULL)
{
display_all = TRUE;
printf("Module: %s\n",MODULE[mi].module);
}
MODULE[mi].func(rstr, REGREAD, 0);
}
return;
}
}
printf(INVMOD,argv[1]);
}
/********************************************************************/
void
cpu_handle_interrupt (int vector)
{
if (vector < 64 || vector > 128)
return;
switch (vector)
{
case 65: /* Eport Interrupt 1 */
MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF1;
printf("\nEdge Port Interrupt #1\n");
break;
case 66: /* Eport Interrupt 4 */
MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF4;
printf("\nEdge Port Interrupt #4\n");
break;
case 67: /* Eport Interrupt 7 */
MCF_EPORT_EPFR = MCF_EPORT_EPFR_EPF7;
printf("\nEdge Port Interrupt #7\n");
break;
default:
printf("\nUser Defined Vector #%d\n",vector);
break;
}
}
/********************************************************************/
/*
* Pause for the specified number of micro-seconds.
* Uses DTIM3 as a timer
*/
void
cpu_pause_usec(int usecs)
{
/* Enable the DMA Timer 3 */
MCF_TIMER3_DTRR = (usecs - 1);
MCF_TIMER3_DTER = MCF_TIMER_DTER_REF;
MCF_TIMER3_DTMR = 0
| MCF_TIMER_DTMR_PS(SYSTEM_CLOCK)
| MCF_TIMER_DTMR_ORRI
| MCF_TIMER_DTMR_FRR
| MCF_TIMER_DTMR_CLK_DIV1
| MCF_TIMER_DTMR_RST;
while ((MCF_TIMER3_DTER & MCF_TIMER_DTER_REF) == 0)
{};
/* Disable the timer */
MCF_TIMER3_DTMR = 0;
}
/********************************************************************/
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