📄 mcf532x_lo.s
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/*
* File: mcf532x_lo.s
* Purpose: Lowest level routines for mcf532x.
*
* Notes:
*
*/
#ifdef _UNDERSCORE_
#define __CORE_SRAM ___CORE_SRAM
#define __CORE_SRAM_SIZE ___CORE_SRAM_SIZE
#define __SP_INIT ___SP_INIT
#define sysinit _sysinit
#define main _main
#define asm_set_ipl _asm_set_ipl
#endif
.extern __CORE_SRAM
.extern __CORE_SRAM_SIZE
.extern __SP_INIT
.extern sysinit
.extern main
.extern asm_set_ipl
.global asm_startmeup
.global _asm_startmeup
.global cpu_cache_flush
.global _cpu_cache_flush
.text
/********************************************************************
* This is the main entry point upon hard reset.
*/
asm_startmeup:
_asm_startmeup:
/* Initialize RAMBAR1: locate SRAM, enable back door, and validate it */
move.l #__CORE_SRAM,d0
add.l #0x221,d0
.long 0x4e7b0C05 /* movec d0,RAMBAR1 */
/* Point Stack Pointer into SRAM temporarily */
move.l #__CORE_SRAM,d0
add.l #__CORE_SRAM_SIZE,d0
move.l d0,sp
/* Initialize mcf5208 periphs, etc */
jsr sysinit
/* Relocate Stack Pointer */
move.l #__SP_INIT,SP
/* Jump to the main process */
#ifdef __GNUC__
jsr dbug_main
#else
jsr main
#endif
bra .
nop
nop
halt
/********************************************************************
* The MCF5208 cache can be configured as instruction, data or split.
* Invalidate the entire cache.
*/
cpu_cache_flush:
_cpu_cache_flush:
nop /* sync */
move.l #0x01000000,d0 /* Invalidate the I-Cache */
movec d0,cacr
rts
.end
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