📄 mpc8xx.h
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typedef volatile struct
{
uint32 SCCRK; /* System Clock Control Key */
uint32 PLPRCRK; /* PLL, Low Power Reset Control Key */
uint32 RSRK; /* Reset, Status Register Key */
uint32 reserved1[(1+0x3ff-0x38c)/4];
/*
uint32 reserved2[(1+0x7ff-0x400)/4];
uint32 reserved3[(1+0x85f-0x800)/4];
*/
} MPC8XX_CLOCKEY;
#define MPC8XX_CLOCKEY_KEY_LOCK (0x00000000)
#define MPC8XX_CLOCKEY_KEY_UNLOCK (0x55CCAA33)
#endif /* Mpc8xx_clockey */
/***********************************************************************/
#ifdef Mpc8xx_i2c
/*
* Inter-Integrated device Communications, I2C
*/
typedef volatile struct
{
uint8 I2MOD; /* I2C Mode Register */
uint8 reserved1[3];
uint8 I2ADD; /* I2C Address Register */
uint8 reserved2[3];
uint8 I2BRG; /* I2C BRG Register */
uint8 reserved3[3];
uint8 I2COM; /* I2C Command Register */
uint8 reserved4[3];
uint8 I2CER; /* I2C Event Register */
uint8 reserved5[3];
uint8 I2CMR; /* I2C Mask Register */
uint8 reserved6[3];
uint32 reserved7[(1+0x8ff-0x878)/4];
} MPC8XX_I2C;
#define MPC8XX_I2C_I2MOD_REVD (0x20)
#define MPC8XX_I2C_I2MOD_GCD (0x10)
#define MPC8XX_I2C_I2MOD_FLT (0x08)
#define MPC8XX_I2C_I2MOD_PDIV_32 (0x00)
#define MPC8XX_I2C_I2MOD_PDIV_16 (0x02)
#define MPC8XX_I2C_I2MOD_PDIV_8 (0x04)
#define MPC8XX_I2C_I2MOD_PDIV_4 (0x06)
#define MPC8XX_I2C_I2MOD_EN (0x01)
#define MPC8XX_I2C_I2ADD_SAD(X) ((X)&0x00FE)
#define MPC8XX_I2C_I2BRG_DIV(X) ((X)&0x00FF)
#define MPC8XX_I2C_I2COM_STR (0x80)
#define MPC8XX_I2C_I2COM_MASTER (0x01)
#define MPC8XX_I2C_I2COM_SLAVE (0x00)
#define MPC8XX_I2C_I2CER_TXE (0x10)
#define MPC8XX_I2C_I2CER_BSY (0x04)
#define MPC8XX_I2C_I2CER_TXB (0x02)
#define MPC8XX_I2C_I2CER_RXB (0x01)
#define MPC8XX_I2C_I2CMR_TXE (0x10)
#define MPC8XX_I2C_I2CMR_BSY (0x04)
#define MPC8XX_I2C_I2CMR_TXB (0x02)
#define MPC8XX_I2C_I2CMR_RXB (0x01)
#endif /* Mpc8xx_i2c */
/***********************************************************************/
#ifdef Mpc8xx_dma
/*
* Directory Memory Access, DMA
*/
typedef volatile struct
{
uint32 reserved1;
uint32 SDAR; /* SDMA Address Register */
uint8 SDSR; /* SDMA Status Register */
uint8 reserved2[3];
uint8 SDMR; /* SDMA Mask Register */
uint8 reserved3[3];
uint8 IDSR1; /* IDMA1 Status Register */
uint8 reserved4[3];
uint8 IDMR1; /* IDMA1 Mask Register */
uint8 reserved5[3];
uint8 IDSR2; /* IDMA2 Status Register */
uint8 reserved6[3];
uint8 IDMR2; /* IDMA2 Mask Register */
uint8 reserved7[3];
uint32 reserved8[(1+0x92f-0x91d)/4];
} MPC8XX_DMA;
#define MPC8XX_DMA_SDSR_SBER (0x80)
#define MPC8XX_DMA_SDSR_RINT (0x40)
#define MPC8XX_DMA_SDSR_DSP2 (0x02)
#define MPC8XX_DMA_SDSR_DSP1 (0x01)
#define MPC8XX_DMA_SDMR_SBER (0x80)
#define MPC8XX_DMA_SDMR_RINT (0x40)
#define MPC8XX_DMA_SDMR_DSP2 (0x02)
#define MPC8XX_DMA_SDMR_DSP1 (0x01)
/* FIX !!! missing DMA_SDSR_xxx */
#endif /* Mpc8xx_dma */
/***********************************************************************/
#ifdef Mpc8xx_cpic
/*
* CPM Interrupt Controller, CPIC
*/
typedef volatile struct
{
uint16 CIVR; /* CP Interrupt Vector Register */
uint16 reserved1[(1+0x93f-0x932)/2];
uint32 CICR; /* Interrupt Configuration Register */
uint32 CIPR; /* Interrupt Pending Register */
uint32 CIMR; /* Interrupt Mask Register */
uint32 CISR; /* In-Service Register */
} MPC8XX_CPIC;
#define MPC8XX_CPIC_CIVR_MASK (0xFF00)
#define MPC8XX_CPIC_CIVR_IACK (0x0001)
#define MPC8XX_CPIC_CICR_SCDP_SCC1 (0x00000000)
#define MPC8XX_CPIC_CICR_SCDP_SCC2 (0x00400000)
#define MPC8XX_CPIC_CICR_SCDP_SCC3 (0x00800000)
#define MPC8XX_CPIC_CICR_SCDP_SCC4 (0x00C00000)
#define MPC8XX_CPIC_CICR_SCCP_SCC1 (0x00000000)
#define MPC8XX_CPIC_CICR_SCCP_SCC2 (0x00100000)
#define MPC8XX_CPIC_CICR_SCCP_SCC3 (0x00200000)
#define MPC8XX_CPIC_CICR_SCCP_SCC4 (0x00300000)
#define MPC8XX_CPIC_CICR_SCBP_SCC1 (0x00000000)
#define MPC8XX_CPIC_CICR_SCBP_SCC2 (0x00040000)
#define MPC8XX_CPIC_CICR_SCBP_SCC3 (0x00080000)
#define MPC8XX_CPIC_CICR_SCBP_SCC4 (0x000C0000)
#define MPC8XX_CPIC_CICR_SCAP_SCC1 (0x00000000)
#define MPC8XX_CPIC_CICR_SCAP_SCC2 (0x00010000)
#define MPC8XX_CPIC_CICR_SCAP_SCC3 (0x00020000)
#define MPC8XX_CPIC_CICR_SCAP_SCC4 (0x00030000)
#define MPC8XX_CPIC_CICR_IRL_0 (0x00000000)
#define MPC8XX_CPIC_CICR_IRL_1 (0x00002000)
#define MPC8XX_CPIC_CICR_IRL_2 (0x00004000)
#define MPC8XX_CPIC_CICR_IRL_3 (0x00006000)
#define MPC8XX_CPIC_CICR_IRL_4 (0x00008000)
#define MPC8XX_CPIC_CICR_IRL_5 (0x0000A000)
#define MPC8XX_CPIC_CICR_IRL_6 (0x0000C000)
#define MPC8XX_CPIC_CICR_IRL_7 (0x0000E000)
#define MPC8XX_CPIC_CICR_HP_1F (0x00001F00)
#define MPC8XX_CPIC_CICR_HP_1E (0x00001E00)
#define MPC8XX_CPIC_CICR_HP_1D (0x00001D00)
#define MPC8XX_CPIC_CICR_HP_1C (0x00001C00)
#define MPC8XX_CPIC_CICR_HP_1B (0x00001B00)
#define MPC8XX_CPIC_CICR_HP_1A (0x00001A00)
#define MPC8XX_CPIC_CICR_HP_19 (0x00001900)
#define MPC8XX_CPIC_CICR_HP_18 (0x00001800)
#define MPC8XX_CPIC_CICR_HP_17 (0x00001700)
#define MPC8XX_CPIC_CICR_HP_16 (0x00001600)
#define MPC8XX_CPIC_CICR_HP_15 (0x00001500)
#define MPC8XX_CPIC_CICR_HP_14 (0x00001400)
#define MPC8XX_CPIC_CICR_HP_13 (0x00001300)
#define MPC8XX_CPIC_CICR_HP_12 (0x00001200)
#define MPC8XX_CPIC_CICR_HP_11 (0x00001100)
#define MPC8XX_CPIC_CICR_HP_10 (0x00001000)
#define MPC8XX_CPIC_CICR_HP_F (0x00000F00)
#define MPC8XX_CPIC_CICR_HP_E (0x00000E00)
#define MPC8XX_CPIC_CICR_HP_D (0x00000D00)
#define MPC8XX_CPIC_CICR_HP_C (0x00000C00)
#define MPC8XX_CPIC_CICR_HP_B (0x00000B00)
#define MPC8XX_CPIC_CICR_HP_A (0x00000A00)
#define MPC8XX_CPIC_CICR_HP_9 (0x00000900)
#define MPC8XX_CPIC_CICR_HP_8 (0x00000800)
#define MPC8XX_CPIC_CICR_HP_7 (0x00000700)
#define MPC8XX_CPIC_CICR_HP_6 (0x00000600)
#define MPC8XX_CPIC_CICR_HP_5 (0x00000500)
#define MPC8XX_CPIC_CICR_HP_4 (0x00000400)
#define MPC8XX_CPIC_CICR_HP_3 (0x00000300)
#define MPC8XX_CPIC_CICR_HP_2 (0x00000200)
#define MPC8XX_CPIC_CICR_HP_1 (0x00000100)
#define MPC8XX_CPIC_CICR_HP_0 (0x00000000)
#define MPC8XX_CPIC_CICR_IEN (0x00000080)
#define MPC8XX_CPIC_CICR_SPS (0x00000001)
#define MPC8XX_CPIC_CIPR_PC15 (0x80000000)
#define MPC8XX_CPIC_CIPR_SCC1 (0x40000000)
#define MPC8XX_CPIC_CIPR_SCC2 (0x20000000)
#define MPC8XX_CPIC_CIPR_SCC3 (0x10000000)
#define MPC8XX_CPIC_CIPR_SCC4 (0x08000000)
#define MPC8XX_CPIC_CIPR_PC14 (0x04000000)
#define MPC8XX_CPIC_CIPR_TIMER1 (0x02000000)
#define MPC8XX_CPIC_CIPR_PC13 (0x01000000)
#define MPC8XX_CPIC_CIPR_PC12 (0x00800000)
#define MPC8XX_CPIC_CIPR_SDMA (0x00400000)
#define MPC8XX_CPIC_CIPR_IDMA1 (0x00200000)
#define MPC8XX_CPIC_CIPR_IDMA2 (0x00100000)
#define MPC8XX_CPIC_CIPR_TIMER2 (0x00040000)
#define MPC8XX_CPIC_CIPR_RTT (0x00020000)
#define MPC8XX_CPIC_CIPR_I2C (0x00010000)
#define MPC8XX_CPIC_CIPR_PC11 (0x00008000)
#define MPC8XX_CPIC_CIPR_PC10 (0x00004000)
#define MPC8XX_CPIC_CIPR_TIMER3 (0x00001000)
#define MPC8XX_CPIC_CIPR_PC9 (0x00000800)
#define MPC8XX_CPIC_CIPR_PC8 (0x00000400)
#define MPC8XX_CPIC_CIPR_PC7 (0x00000200)
#define MPC8XX_CPIC_CIPR_TIMER4 (0x00000080)
#define MPC8XX_CPIC_CIPR_PC6 (0x00000040)
#define MPC8XX_CPIC_CIPR_SPI (0x00000020)
#define MPC8XX_CPIC_CIPR_SMC1 (0x00000010)
#define MPC8XX_CPIC_CIPR_SMC2 (0x00000008)
#define MPC8XX_CPIC_CIPR_PIP (0x00000008)
#define MPC8XX_CPIC_CIPR_PC5 (0x00000004)
#define MPC8XX_CPIC_CIPR_PC4 (0x00000002)
#define MPC8XX_CPIC_CIMR_PC15 (0x80000000)
#define MPC8XX_CPIC_CIMR_SCC1 (0x40000000)
#define MPC8XX_CPIC_CIMR_SCC2 (0x20000000)
#define MPC8XX_CPIC_CIMR_SCC3 (0x10000000)
#define MPC8XX_CPIC_CIMR_SCC4 (0x08000000)
#define MPC8XX_CPIC_CIMR_PC14 (0x04000000)
#define MPC8XX_CPIC_CIMR_TIMER1 (0x02000000)
#define MPC8XX_CPIC_CIMR_PC13 (0x01000000)
#define MPC8XX_CPIC_CIMR_PC12 (0x00800000)
#define MPC8XX_CPIC_CIMR_SDMA (0x00400000)
#define MPC8XX_CPIC_CIMR_IDMA1 (0x00200000)
#define MPC8XX_CPIC_CIMR_IDMA2 (0x00100000)
#define MPC8XX_CPIC_CIMR_TIMER2 (0x00040000)
#define MPC8XX_CPIC_CIMR_RTT (0x00020000)
#define MPC8XX_CPIC_CIMR_I2C (0x00010000)
#define MPC8XX_CPIC_CIMR_PC11 (0x00008000)
#define MPC8XX_CPIC_CIMR_PC10 (0x00004000)
#define MPC8XX_CPIC_CIMR_TIMER3 (0x00001000)
#define MPC8XX_CPIC_CIMR_PC9 (0x00000800)
#define MPC8XX_CPIC_CIMR_PC8 (0x00000400)
#define MPC8XX_CPIC_CIMR_PC7 (0x00000200)
#define MPC8XX_CPIC_CIMR_TIMER4 (0x00000080)
#define MPC8XX_CPIC_CIMR_PC6 (0x00000040)
#define MPC8XX_CPIC_CIMR_SPI (0x00000020)
#define MPC8XX_CPIC_CIMR_SMC1 (0x00000010)
#define MPC8XX_CPIC_CIMR_SMC2 (0x00000008)
#define MPC8XX_CPIC_CIMR_PIP (0x00000008)
#define MPC8XX_CPIC_CIMR_PC5 (0x00000004)
#define MPC8XX_CPIC_CIMR_PC4 (0x00000002)
#define MPC8XX_CPIC_CISR_PC15 (0x80000000)
#define MPC8XX_CPIC_CISR_SCC1 (0x40000000)
#define MPC8XX_CPIC_CISR_SCC2 (0x20000000)
#define MPC8XX_CPIC_CISR_SCC3 (0x10000000)
#define MPC8XX_CPIC_CISR_SCC4 (0x08000000)
#define MPC8XX_CPIC_CISR_PC14 (0x04000000)
#define MPC8XX_CPIC_CISR_TIMER1 (0x02000000)
#define MPC8XX_CPIC_CISR_PC13 (0x01000000)
#define MPC8XX_CPIC_CISR_PC12 (0x00800000)
#define MPC8XX_CPIC_CISR_SDMA (0x00400000)
#define MPC8XX_CPIC_CISR_IDMA1 (0x00200000)
#define MPC8XX_CPIC_CISR_IDMA2 (0x00100000)
#define MPC8XX_CPIC_CISR_TIMER2 (0x00040000)
#define MPC8XX_CPIC_CISR_RTT (0x00020000)
#define MPC8XX_CPIC_CISR_I2C (0x00010000)
#define MPC8XX_CPIC_CISR_PC11 (0x00008000)
#define MPC8XX_CPIC_CISR_PC10 (0x00004000)
#define MPC8XX_CPIC_CISR_TIMER3 (0x00001000)
#define MPC8XX_CPIC_CISR_PC9 (0x00000800)
#define MPC8XX_CPIC_CISR_PC8 (0x00000400)
#define MPC8XX_CPIC_CISR_PC7 (0x00000200)
#define MPC8XX_CPIC_CISR_TIMER4 (0x00000080)
#define MPC8XX_CPIC_CISR_PC6 (0x00000040)
#define MPC8XX_CPIC_CISR_SPI (0x00000020)
#define MPC8XX_CPIC_CISR_SMC1 (0x00000010)
#define MPC8XX_CPIC_CISR_SMC2 (0x00000008)
#define MPC8XX_CPIC_CISR_PIP (0x00000008)
#define MPC8XX_CPIC_CISR_PC5 (0x00000004)
#define MPC8XX_CPIC_CISR_PC4 (0x00000002)
#endif /* Mpc8xx_cpic */
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