📄 mpc8xx.h
字号:
#define MPC8XX_MEMC_MCR_MCLF_5 (0x00000500)
#define MPC8XX_MEMC_MCR_MCLF_6 (0x00000600)
#define MPC8XX_MEMC_MCR_MCLF_7 (0x00000700)
#define MPC8XX_MEMC_MCR_MCLF_8 (0x00000800)
#define MPC8XX_MEMC_MCR_MCLF_9 (0x00000900)
#define MPC8XX_MEMC_MCR_MCLF_10 (0x00000A00)
#define MPC8XX_MEMC_MCR_MCLF_11 (0x00000B00)
#define MPC8XX_MEMC_MCR_MCLF_12 (0x00000C00)
#define MPC8XX_MEMC_MCR_MCLF_13 (0x00000D00)
#define MPC8XX_MEMC_MCR_MCLF_14 (0x00000E00)
#define MPC8XX_MEMC_MCR_MCLF_15 (0x00000F00)
#define MPC8XX_MEMC_MCR_MCLF_16 (0x00000000)
#define MPC8XX_MEMC_MCR_MAD_N(N) ((N) & 0x3F)
#define MPC8XX_MEMC_MMR_PT(a) (((a)&0x00FF)<<24)
#define MPC8XX_MEMC_MMR_PTE (0x00800000)
#define MPC8XX_MEMC_MMR_AM_MASK (0x00700000)
#define MPC8XX_MEMC_MMR_AM_000 (0x00000000)
#define MPC8XX_MEMC_MMR_AM_001 (0x00100000)
#define MPC8XX_MEMC_MMR_AM_010 (0x00200000)
#define MPC8XX_MEMC_MMR_AM_011 (0x00300000)
#define MPC8XX_MEMC_MMR_AM_100 (0x00400000)
#define MPC8XX_MEMC_MMR_AM_101 (0x00500000)
#define MPC8XX_MEMC_MMR_DS_1 (0x00000000)
#define MPC8XX_MEMC_MMR_DS_2 (0x00020000)
#define MPC8XX_MEMC_MMR_DS_3 (0x00040000)
#define MPC8XX_MEMC_MMR_DS_4 (0x00060000)
#define MPC8XX_MEMC_MMR_G0CL_A12 (0x00000000)
#define MPC8XX_MEMC_MMR_G0CL_A11 (0x00002000)
#define MPC8XX_MEMC_MMR_G0CL_A10 (0x00004000)
#define MPC8XX_MEMC_MMR_G0CL_A9 (0x00006000)
#define MPC8XX_MEMC_MMR_G0CL_A8 (0x00008000)
#define MPC8XX_MEMC_MMR_G0CL_A7 (0x0000A000)
#define MPC8XX_MEMC_MMR_G0CL_A6 (0x0000C000)
#define MPC8XX_MEMC_MMR_G0CL_A5 (0x0000E000)
#define MPC8XX_MEMC_MMR_GPL_4DIS (0x00001000)
#define MPC8XX_MEMC_MMR_RLF_1 (0x00000100)
#define MPC8XX_MEMC_MMR_RLF_2 (0x00000200)
#define MPC8XX_MEMC_MMR_RLF_3 (0x00000300)
#define MPC8XX_MEMC_MMR_RLF_4 (0x00000400)
#define MPC8XX_MEMC_MMR_RLF_5 (0x00000500)
#define MPC8XX_MEMC_MMR_RLF_6 (0x00000600)
#define MPC8XX_MEMC_MMR_RLF_7 (0x00000700)
#define MPC8XX_MEMC_MMR_RLF_8 (0x00000800)
#define MPC8XX_MEMC_MMR_RLF_9 (0x00000900)
#define MPC8XX_MEMC_MMR_RLF_10 (0x00000A00)
#define MPC8XX_MEMC_MMR_RLF_11 (0x00000B00)
#define MPC8XX_MEMC_MMR_RLF_12 (0x00000C00)
#define MPC8XX_MEMC_MMR_RLF_13 (0x00000D00)
#define MPC8XX_MEMC_MMR_RLF_14 (0x00000E00)
#define MPC8XX_MEMC_MMR_RLF_15 (0x00000F00)
#define MPC8XX_MEMC_MMR_RLF_16 (0x00000000)
#define MPC8XX_MEMC_MMR_WLF_1 (0x00000010)
#define MPC8XX_MEMC_MMR_WLF_2 (0x00000020)
#define MPC8XX_MEMC_MMR_WLF_3 (0x00000030)
#define MPC8XX_MEMC_MMR_WLF_4 (0x00000040)
#define MPC8XX_MEMC_MMR_WLF_5 (0x00000050)
#define MPC8XX_MEMC_MMR_WLF_6 (0x00000060)
#define MPC8XX_MEMC_MMR_WLF_7 (0x00000070)
#define MPC8XX_MEMC_MMR_WLF_8 (0x00000080)
#define MPC8XX_MEMC_MMR_WLF_9 (0x00000090)
#define MPC8XX_MEMC_MMR_WLF_10 (0x000000A0)
#define MPC8XX_MEMC_MMR_WLF_11 (0x000000B0)
#define MPC8XX_MEMC_MMR_WLF_12 (0x000000C0)
#define MPC8XX_MEMC_MMR_WLF_13 (0x000000D0)
#define MPC8XX_MEMC_MMR_WLF_14 (0x000000E0)
#define MPC8XX_MEMC_MMR_WLF_15 (0x000000F0)
#define MPC8XX_MEMC_MMR_WLF_16 (0x00000000)
#define MPC8XX_MEMC_MMR_TLF_1 (0x00000001)
#define MPC8XX_MEMC_MMR_TLF_2 (0x00000002)
#define MPC8XX_MEMC_MMR_TLF_3 (0x00000003)
#define MPC8XX_MEMC_MMR_TLF_4 (0x00000004)
#define MPC8XX_MEMC_MMR_TLF_5 (0x00000005)
#define MPC8XX_MEMC_MMR_TLF_6 (0x00000006)
#define MPC8XX_MEMC_MMR_TLF_7 (0x00000007)
#define MPC8XX_MEMC_MMR_TLF_8 (0x00000008)
#define MPC8XX_MEMC_MMR_TLF_9 (0x00000009)
#define MPC8XX_MEMC_MMR_TLF_10 (0x0000000A)
#define MPC8XX_MEMC_MMR_TLF_11 (0x0000000B)
#define MPC8XX_MEMC_MMR_TLF_12 (0x0000000C)
#define MPC8XX_MEMC_MMR_TLF_13 (0x0000000D)
#define MPC8XX_MEMC_MMR_TLF_14 (0x0000000E)
#define MPC8XX_MEMC_MMR_TLF_15 (0x0000000F)
#define MPC8XX_MEMC_MMR_TLF_16 (0x00000000)
#define MPC8XX_MEMC_MSTAT_PER0 (0x8000)
#define MPC8XX_MEMC_MSTAT_PER1 (0x4000)
#define MPC8XX_MEMC_MSTAT_PER2 (0x2000)
#define MPC8XX_MEMC_MSTAT_PER3 (0x1000)
#define MPC8XX_MEMC_MSTAT_PER4 (0x0800)
#define MPC8XX_MEMC_MSTAT_PER5 (0x0400)
#define MPC8XX_MEMC_MSTAT_PER6 (0x0200)
#define MPC8XX_MEMC_MSTAT_PER7 (0x0100)
#define MPC8XX_MEMC_MSTAT_WPER (0x0080)
#define MPC8XX_MEMC_MPTPR_PTP_1 (0x4000)
#define MPC8XX_MEMC_MPTPR_PTP_2 (0x2000)
#define MPC8XX_MEMC_MPTPR_PTP_4 (0x1000)
#define MPC8XX_MEMC_MPTPR_PTP_8 (0x0800)
#define MPC8XX_MEMC_MPTPR_PTP_16 (0x0400)
#define MPC8XX_MEMC_MPTPR_PTP_32 (0x0200)
#define MPC8XX_MEMC_MPTPR_PTP_64 (0x0100)
#endif /* Mpc8xx_memc */
/***********************************************************************/
#ifdef Mpc8xx_sit
/*
* System Integration Timers, SIT
*/
typedef volatile struct
{
uint16 TBSCR; /* Time Base Status and Control */
uint16 reserved1;
uint32 TBREFF0; /* Time Base Reference 0 */
uint32 TBREFF1; /* Time Base Reference 1 */
uint32 reserved2[(1+0x21f-0x20c)/4];
uint16 RTCSC; /* Real Time Clock Status and Control */
uint16 reserved3;
uint32 RTC; /* Real Time Clock */
uint32 RTSEC; /* Real Time Alarm Seconds */
uint32 RTCAL; /* Real Time Alarm */
uint32 reserved4[(1+0x23f-0x230)/4];
uint16 PISCR; /* PIT Status and Control */
uint16 reserved5;
uint32 PITC; /* PIT Count */
uint32 PITR; /* PIT */
uint32 reserved6[(1+0x27f-0x24c)/4];
} MPC8XX_SIT;
#define MPC8XX_SIT_TBSCR_TBIRQ(a) (((a)&0x00FF)<<8)
#define MPC8XX_SIT_TBSCR_REFA (0x0080)
#define MPC8XX_SIT_TBSCR_REFB (0x0040)
#define MPC8XX_SIT_TBSCR_REFAE (0x0008)
#define MPC8XX_SIT_TBSCR_REFBE (0x0004)
#define MPC8XX_SIT_TBSCR_TBF (0x0002)
#define MPC8XX_SIT_TBSCR_TBE (0x0001)
#define MPC8XX_SIT_RTCSC_RTCIRQ(a) (((a)&0x00FF)<<8)
#define MPC8XX_SIT_RTCSC_SEC (0x0080)
#define MPC8XX_SIT_RTCSC_ALR (0x0040)
#define MPC8XX_SIT_RTCSC_38K (0x0010)
#define MPC8XX_SIT_RTCSC_SIE (0x0008)
#define MPC8XX_SIT_RTCSC_ALE (0x0004)
#define MPC8XX_SIT_RTCSC_RTF (0x0002)
#define MPC8XX_SIT_RTCSC_RTE (0x0001)
#define MPC8XX_SIT_PISCR_PIRQ(a) (((a)&0x00FF)<<8)
#define MPC8XX_SIT_PISCR_PS (0x0080)
#define MPC8XX_SIT_PISCR_PIE (0x0004)
#define MPC8XX_SIT_PISCR_PITF (0x0002)
#define MPC8XX_SIT_PISCR_PTE (0x0001)
#endif /* Mpc8xx_sit */
/***********************************************************************/
#ifdef Mpc8xx_clock
/*
* Clocks and Resets, CLOCK
*/
typedef volatile struct
{
uint32 SCCR; /* System Clock Control */
uint32 PLPRCR; /* PLL, Low Power and Reset Control */
uint32 RSR; /* Reset Status Register */
uint32 reserved[(1+0x2ff-0x28c)/4];
} MPC8XX_CLOCK;
#define MPC8XX_CLOCK_SCCR_COM (0x60000000)
#define MPC8XX_CLOCK_SCCR_COM_FULL (0x00000000)
#define MPC8XX_CLOCK_SCCR_COM_HALF (0x20000000)
#define MPC8XX_CLOCK_SCCR_COM_NONE (0x60000000)
#define MPC8XX_CLOCK_SCCR_TBS (0x02000000)
#define MPC8XX_CLOCK_SCCR_TBS_OSCCLK (0x00000000)
#define MPC8XX_CLOCK_SCCR_TBS_SYSCLK (0x02000000)
#define MPC8XX_CLOCK_SCCR_RTDIV (0x01000000)
#define MPC8XX_CLOCK_SCCR_RTDIV_4 (0x00000000)
#define MPC8XX_CLOCK_SCCR_RTDIV_512 (0x01000000)
#define MPC8XX_CLOCK_SCCR_RTSEL (0x00800000)
#define MPC8XX_CLOCK_SCCR_RTSEL_OSCM (0x00000000)
#define MPC8XX_CLOCK_SCCR_RTSEL_EXTCLK (0x00800000)
#define MPC8XX_CLOCK_SCCR_CRQEN (0x00400000)
#define MPC8XX_CLOCK_SCCR_CRQEN_LOWF (0x00000000)
#define MPC8XX_CLOCK_SCCR_CRQEN_HIGHF (0x00400000)
#define MPC8XX_CLOCK_SCCR_PRQEN (0x00200000)
#define MPC8XX_CLOCK_SCCR_PRQEN_LOWF (0x00000000)
#define MPC8XX_CLOCK_SCCR_PRQEN_HIGHF (0x00200000)
#define MPC8XX_CLOCK_SCCR_EBDF (0x00060000)
#define MPC8XX_CLOCK_SCCR_EBDF_GCLK2_DIV_1 (0x00000000)
#define MPC8XX_CLOCK_SCCR_EBDF_GCLK2_DIV_2 (0x00020000)
#define MPC8XX_CLOCK_SCCR_DFSYNC (0x00006000)
#define MPC8XX_CLOCK_SCCR_DFSYNC_DIV_1 (0x00000000)
#define MPC8XX_CLOCK_SCCR_DFSYNC_DIV_4 (0x00002000)
#define MPC8XX_CLOCK_SCCR_DFSYNC_DIV_16 (0x00004000)
#define MPC8XX_CLOCK_SCCR_DFSYNC_DIV_64 (0x00006000)
#define MPC8XX_CLOCK_SCCR_DFBRG (0x00001800)
#define MPC8XX_CLOCK_SCCR_DFBRG_DIV_1 (0x00000000)
#define MPC8XX_CLOCK_SCCR_DFBRG_DIV_4 (0x00000800)
#define MPC8XX_CLOCK_SCCR_DFBRG_DIV_16 (0x00001000)
#define MPC8XX_CLOCK_SCCR_DFBRG_DIV_64 (0x00001800)
#define MPC8XX_CLOCK_SCCR_DFNL (0x00000700)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_2 (0x00000000)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_4 (0x00000100)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_8 (0x00000200)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_16 (0x00000300)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_32 (0x00000400)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_64 (0x00000500)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_256 (0x00000700)
#define MPC8XX_CLOCK_SCCR_DFNH (0x000000E0)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_1 (0x00000000)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_2 (0x00000020)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_4 (0x00000040)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_8 (0x00000060)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_16 (0x00000080)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_32 (0x000000A0)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_64 (0x000000E0)
#define MPC8XX_CLOCK_PLPRCR_MF (0xFFF00000)
#define MPC8XX_CLOCK_PLPRCR_MF_N(a) (((a)&0x00000FFF) << 20)
#define MPC8XX_CLOCK_PLPRCR_SPLSS (0x00008000)
#define MPC8XX_CLOCK_PLPRCR_TEXPS (0x00004000)
#define MPC8XX_CLOCK_PLPRCR_TMIST (0x00001000)
#define MPC8XX_CLOCK_PLPRCR_CSRC_DFNH (0x00000000)
#define MPC8XX_CLOCK_PLPRCR_CSRC_DFNL (0x00000400)
#define MPC8XX_CLOCK_PLPRCR_LPM_00 (0x00000000)
#define MPC8XX_CLOCK_PLPRCR_LPM_01 (0x00000100)
#define MPC8XX_CLOCK_PLPRCR_LPM_10 (0x00000200)
#define MPC8XX_CLOCK_PLPRCR_LPM_11 (0x00000300)
#define MPC8XX_CLOCK_PLPRCR_CSR (0x00000080)
#define MPC8XX_CLOCK_PLPRCR_LOLRE (0x00000040)
#define MPC8XX_CLOCK_PLPRCR_FIOPD (0x00000020)
#define MPC8XX_CLOCK_RSR_EHRS (0x80000000)
#define MPC8XX_CLOCK_RSR_ESRS (0x40000000)
#define MPC8XX_CLOCK_RSR_LLRS (0x20000000)
#define MPC8XX_CLOCK_RSR_SWRS (0x10000000)
#define MPC8XX_CLOCK_RSR_SCRS (0x08000000)
#define MPC8XX_CLOCK_RSR_DBSRS (0x04000000)
#define MPC8XX_CLOCK_RSR_JTRS (0x02000000)
#endif /* Mpc8xx_clock */
/***********************************************************************/
#ifdef Mpc8xx_sitkey
/*
* System Integration Timers Keys, SITKEY
*/
typedef volatile struct
{
uint32 TBSCRK; /* Time Base Status and Control Key */
uint32 TBREFF0K; /* Time Base Reference 0 Key */
uint32 TBREFF1K; /* Time Base Reference 1 Key */
uint32 TBK; /* Time Base and Decrementer Key */
uint32 reserved1[(1+0x31f-0x310)/4];
uint32 RTCSCK; /* Real Time Clock Status and Control */
uint32 RTCK; /* Real Time Clock Key */
uint32 RTSECK; /* Real Time Alarm Seconds Key */
uint32 RTCALK; /* Real Time Alarm Key */
uint32 reserved2[(1+0x33f-0x330)/4];
uint32 PISCRK; /* PIT Status and Control Key */
uint32 PITCK; /* PIT Count Key */
uint32 reserved3[(1+0x37f-0x348)/4];
} MPC8XX_SITKEY;
#define MPC8XX_SITKEY_KEY_LOCK (0x00000000)
#define MPC8XX_SITKEY_KEY_UNLOCK (0x55CCAA33)
#endif /* Mpc8xx_sitkey */
/***********************************************************************/
#ifdef Mpc8xx_clockey
/*
* Clocks and Resets Keys, CLOCKEY
*/
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -