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📄 mpc8xx.h

📁 motorola 针对coldfire 5275 评估板的Dbug bootloader源程序
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/*
 * File:        mpc8xx.h
 * Purpose:     Definitions common across all MPC8XX processors
 *
 * Notes:
 *
 *
 * Modifications:
 *
 */

#ifndef _CPU_MPC8XX_H
#define _CPU_MPC8XX_H

/***********************************************************************/

#define MPC8XX_MSR_POW                  (0x00040000)
#define MPC8XX_MSR_ISF                  (0x00020000)
#define MPC8XX_MSR_ILE                  (0x00010000)
#define MPC8XX_MSR_EE                   (0x00008000)
#define MPC8XX_MSR_PR                   (0x00004000)
#define MPC8XX_MSR_FP                   (0x00002000)
#define MPC8XX_MSR_ME                   (0x00001000)
#define MPC8XX_MSR_FE0                  (0x00000800)
#define MPC8XX_MSR_SE                   (0x00000400)
#define MPC8XX_MSR_BE                   (0x00000200)
#define MPC8XX_MSR_FE1                  (0x00000100)
#define MPC8XX_MSR_IP                   (0x00000040)
#define MPC8XX_MSR_IR                   (0x00000020)
#define MPC8XX_MSR_DR                   (0x00000010)
#define MPC8XX_MSR_RI                   (0x00000002)
#define MPC8XX_MSR_LE                   (0x00000001)

#define MPC8XX_IC_CST_IEN               (0x80000000)
#define MPC8XX_IC_CST_CMD_ENABLE        (0x02000000)
#define MPC8XX_IC_CST_CMD_DISABLE       (0x04000000)
#define MPC8XX_IC_CST_CMD_LOCKLINE      (0x06000000)
#define MPC8XX_IC_CST_CMD_UNLOCKLINE    (0x08000000)
#define MPC8XX_IC_CST_CMD_UNLOCKALL     (0x0A000000)
#define MPC8XX_IC_CST_CMD_INVALIDATE    (0x0C000000)
#define MPC8XX_IC_CST_CCER1             (0x00200000)
#define MPC8XX_IC_CST_CCER2             (0x00100000)
#define MPC8XX_IC_CST_CCER3             (0x00080000)

#define MPC8XX_DC_CST_IEN               (0x80000000)
#define MPC8XX_DC_CST_DFWT              (0x40000000)
#define MPC8XX_DC_CST_LES               (0x20000000)
#define MPC8XX_DC_CST_CMD_ENABLE        (0x02000000)
#define MPC8XX_DC_CST_CMD_DISABLE       (0x04000000)
#define MPC8XX_DC_CST_CMD_LOCKLINE      (0x06000000)
#define MPC8XX_DC_CST_CMD_UNLOCKLINE    (0x08000000)
#define MPC8XX_DC_CST_CMD_UNLOCKALL     (0x0A000000)
#define MPC8XX_DC_CST_CMD_INVALIDATE    (0x0C000000)
#define MPC8XX_DC_CST_CMD_FLUSHLINE     (0x0E000000)
#define MPC8XX_DC_CST_CMD_FORCEWRTHRU   (0x01000000)
#define MPC8XX_DC_CST_CMD_NOFORCEWRTHRU (0x03000000)
#define MPC8XX_DC_CST_CMD_LES           (0x05000000)
#define MPC8XX_DC_CST_CMD_NOLES         (0x07000000)
#define MPC8XX_DC_CST_CCER1             (0x00200000)
#define MPC8XX_DC_CST_CCER2             (0x00100000)
#define MPC8XX_DC_CST_CCER3             (0x00080000)

/***********************************************************************/
#ifdef Mpc8xx_siu

/*
 * System Interface Unit, SIU
 */
typedef volatile struct
{
    uint32  SIUMCR;     /* SIUI Module Configuration            */
    uint32  SYPCR;      /* System Protection Control            */
    uint32  SWT;        /* Software Watchdog Timer Current Value*/
    uint16  reserved0;
    uint16  SWSR;       /* Software Service                     */
    uint32  SIPEND;     /* Interrupt Pending Register           */
    uint32  SIMASK;     /* Interrupt Mask Register              */
    uint32  SIEL;       /* Interrupt Edge/Level Mask Register   */
    uint32  SIVEC;      /* Interrupt Vector Register            */
    uint32  TESR;       /* Transfer Error Status Register       */
    uint32  reserved2[(1+0x02f-0x024)/4];
    uint32  SDCR;       /* SDMA Configuration Register          */
    uint32  reserved3[(1+0x07f-0x034)/4];
} MPC8XX_SIU;

#define MPC8XX_SIU_SIUMCR_EARB      (0x80000000)
#define MPC8XX_SIU_SIUMCR_EARP_0    (0x00000000)
#define MPC8XX_SIU_SIUMCR_EARP_1    (0x10000000)
#define MPC8XX_SIU_SIUMCR_EARP_2    (0x20000000)
#define MPC8XX_SIU_SIUMCR_EARP_3    (0x30000000)
#define MPC8XX_SIU_SIUMCR_EARP_4    (0x40000000)
#define MPC8XX_SIU_SIUMCR_EARP_5    (0x50000000)
#define MPC8XX_SIU_SIUMCR_EARP_6    (0x60000000)
#define MPC8XX_SIU_SIUMCR_EARP_7    (0x70000000)
#define MPC8XX_SIU_SIUMCR_DSHW      (0x00800000)
#define MPC8XX_SIU_SIUMCR_DBGC_00   (0x00000000)
#define MPC8XX_SIU_SIUMCR_DBGC_01   (0x00200000)
#define MPC8XX_SIU_SIUMCR_DBGC_11   (0x00600000)
#define MPC8XX_SIU_SIUMCR_DBPC_00   (0x00000000)
#define MPC8XX_SIU_SIUMCR_DBPC_01   (0x00080000)
#define MPC8XX_SIU_SIUMCR_DBPC_11   (0x00180000)
#define MPC8XX_SIU_SIUMCR_FRC       (0x00020000)
#define MPC8XX_SIU_SIUMCR_DLK       (0x00010000)
#define MPC8XX_SIU_SIUMCR_PNCS      (0x00008000)
#define MPC8XX_SIU_SIUMCR_OPAR      (0x00004000)
#define MPC8XX_SIU_SIUMCR_DPC       (0x00002000)
#define MPC8XX_SIU_SIUMCR_MPRE      (0x00001000)
#define MPC8XX_SIU_SIUMCR_MLRC_00   (0x00000000)
#define MPC8XX_SIU_SIUMCR_MLRC_01   (0x00000400)
#define MPC8XX_SIU_SIUMCR_MLRC_10   (0x00000800)
#define MPC8XX_SIU_SIUMCR_MLRC_11   (0x00000C00)
#define MPC8XX_SIU_SIUMCR_MLRC_MASK (0x00000C00)
#define MPC8XX_SIU_SIUMCR_AEME      (0x00000200)
#define MPC8XX_SIU_SIUMCR_SEME      (0x00000100)
#define MPC8XX_SIU_SIUMCR_BSC       (0x00000080)
#define MPC8XX_SIU_SIUMCR_GB5E      (0x00000040)
#define MPC8XX_SIU_SIUMCR_B2DD      (0x00000020)
#define MPC8XX_SIU_SIUMCR_B3DD      (0x00000010)

#define MPC8XX_SIU_SYPCR_SWTC(a)    (((a)&0x0000FFFF)<<16)
#define MPC8XX_SIU_SYPCR_BMT(a)     (((a)&0x000000FF)<<8)
#define MPC8XX_SIU_SYPCR_BME        (0x00000080)
#define MPC8XX_SIU_SYPCR_SWF        (0x00000008)
#define MPC8XX_SIU_SYPCR_SWE        (0x00000004)
#define MPC8XX_SIU_SYPCR_SWRI       (0x00000002)
#define MPC8XX_SIU_SYPCR_SWP        (0x00000001)

#define MPC8XX_SIU_TESR_IEXT        (0x00002000)
#define MPC8XX_SIU_TESR_IBM         (0x00001000)
#define MPC8XX_SIU_TESR_IPB0        (0x00000800)
#define MPC8XX_SIU_TESR_IPB1        (0x00000400)
#define MPC8XX_SIU_TESR_IPB2        (0x00000200)
#define MPC8XX_SIU_TESR_IPB3        (0x00000100)
#define MPC8XX_SIU_TESR_DEXT        (0x00000020)
#define MPC8XX_SIU_TESR_DBM         (0x00000010)
#define MPC8XX_SIU_TESR_DPB0        (0x00000008)
#define MPC8XX_SIU_TESR_DPB1        (0x00000004)
#define MPC8XX_SIU_TESR_DPB2        (0x00000002)
#define MPC8XX_SIU_TESR_DPB3        (0x00000001)

#define MPC8XX_SIU_SIPEND_IRQ0      (0x80000000)
#define MPC8XX_SIU_SIPEND_LVL0      (0x40000000)
#define MPC8XX_SIU_SIPEND_IRQ1      (0x20000000)
#define MPC8XX_SIU_SIPEND_LVL1      (0x10000000)
#define MPC8XX_SIU_SIPEND_IRQ2      (0x08000000)
#define MPC8XX_SIU_SIPEND_LVL2      (0x04000000)
#define MPC8XX_SIU_SIPEND_IRQ3      (0x02000000)
#define MPC8XX_SIU_SIPEND_LVL3      (0x01000000)
#define MPC8XX_SIU_SIPEND_IRQ4      (0x00800000)
#define MPC8XX_SIU_SIPEND_LVL4      (0x00400000)
#define MPC8XX_SIU_SIPEND_IRQ5      (0x00200000)
#define MPC8XX_SIU_SIPEND_LVL5      (0x00100000)
#define MPC8XX_SIU_SIPEND_IRQ6      (0x00080000)
#define MPC8XX_SIU_SIPEND_LVL6      (0x00040000)
#define MPC8XX_SIU_SIPEND_IRQ7      (0x00020000)
#define MPC8XX_SIU_SIPEND_LVL7      (0x00010000)

#define MPC8XX_SIU_SIMASK_IRM0      (0x80000000)
#define MPC8XX_SIU_SIMASK_LVM0      (0x40000000)
#define MPC8XX_SIU_SIMASK_IRM1      (0x20000000)
#define MPC8XX_SIU_SIMASK_LVM1      (0x10000000)
#define MPC8XX_SIU_SIMASK_IRM2      (0x08000000)
#define MPC8XX_SIU_SIMASK_LVM2      (0x04000000)
#define MPC8XX_SIU_SIMASK_IRM3      (0x02000000)
#define MPC8XX_SIU_SIMASK_LVM3      (0x01000000)
#define MPC8XX_SIU_SIMASK_IRM4      (0x00800000)
#define MPC8XX_SIU_SIMASK_LVM4      (0x00400000)
#define MPC8XX_SIU_SIMASK_IRM5      (0x00200000)
#define MPC8XX_SIU_SIMASK_LVM5      (0x00100000)
#define MPC8XX_SIU_SIMASK_IRM6      (0x00080000)
#define MPC8XX_SIU_SIMASK_LVM6      (0x00040000)
#define MPC8XX_SIU_SIMASK_IRM7      (0x00020000)
#define MPC8XX_SIU_SIMASK_LVM7      (0x00010000)

#define MPC8XX_SIU_SIEL_ED0     (0x80000000)
#define MPC8XX_SIU_SIEL_WM0     (0x40000000)
#define MPC8XX_SIU_SIEL_ED1     (0x20000000)
#define MPC8XX_SIU_SIEL_WM1     (0x10000000)
#define MPC8XX_SIU_SIEL_ED2     (0x08000000)
#define MPC8XX_SIU_SIEL_WM2     (0x04000000)
#define MPC8XX_SIU_SIEL_ED3     (0x02000000)
#define MPC8XX_SIU_SIEL_WM3     (0x01000000)
#define MPC8XX_SIU_SIEL_ED4     (0x00800000)
#define MPC8XX_SIU_SIEL_WM4     (0x00400000)
#define MPC8XX_SIU_SIEL_ED5     (0x00200000)
#define MPC8XX_SIU_SIEL_WM5     (0x00100000)
#define MPC8XX_SIU_SIEL_ED6     (0x00080000)
#define MPC8XX_SIU_SIEL_WM6     (0x00040000)
#define MPC8XX_SIU_SIEL_ED7     (0x00020000)
#define MPC8XX_SIU_SIEL_WM7     (0x00010000)

#define MPC8XX_SIU_IC_IRQ_0     (0x00)  /* Interrupt Codes */
#define MPC8XX_SIU_IC_LEVEL_0   (0x04)  /* To be used with IRQ macros */
#define MPC8XX_SIU_IC_IRQ_1     (0x08)
#define MPC8XX_SIU_IC_LEVEL_1   (0x0C)
#define MPC8XX_SIU_IC_IRQ_2     (0x10)
#define MPC8XX_SIU_IC_LEVEL_2   (0x14)
#define MPC8XX_SIU_IC_IRQ_3     (0x18)
#define MPC8XX_SIU_IC_LEVEL_3   (0x1C)
#define MPC8XX_SIU_IC_IRQ_4     (0x20)
#define MPC8XX_SIU_IC_LEVEL_4   (0x24)
#define MPC8XX_SIU_IC_IRQ_5     (0x28)
#define MPC8XX_SIU_IC_LEVEL_5   (0x3C)
#define MPC8XX_SIU_IC_IRQ_6     (0x30)
#define MPC8XX_SIU_IC_LEVEL_6   (0x34)
#define MPC8XX_SIU_IC_IRQ_7     (0x38)
#define MPC8XX_SIU_IC_LEVEL_7   (0x3C)

#define MPC8XX_SIU_SDCR_FRZ_IGNORE  (0x00000000)
#define MPC8XX_SIU_SDCR_FRZ_FORCE   (0x00004000)
#define MPC8XX_SIU_SDCR_RAID_6      (0x00000000)
#define MPC8XX_SIU_SDCR_RAID_5      (0x00000001)
#define MPC8XX_SIU_SDCR_RAID_2      (0x00000002)
#define MPC8XX_SIU_SDCR_RAID_1      (0x00000003)

#endif /* Mpc8xx_siu */

/***********************************************************************/
#ifdef Mpc8xx_pcmcia

/*
 * PCMCIA
 */
typedef volatile struct
{
    uint32  PBR0;       /* PCMCIA Base Register                 */
    uint32  POR0;       /* PCMCIA Option Register               */
    uint32  PBR1;       /* PCMCIA Base Register                 */
    uint32  POR1;       /* PCMCIA Option Register               */
    uint32  PBR2;       /* PCMCIA Base Register                 */
    uint32  POR2;       /* PCMCIA Option Register               */
    uint32  PBR3;       /* PCMCIA Base Register                 */
    uint32  POR3;       /* PCMCIA Option Register               */
    uint32  PBR4;       /* PCMCIA Base Register                 */
    uint32  POR4;       /* PCMCIA Option Register               */
    uint32  PBR5;       /* PCMCIA Base Register                 */
    uint32  POR5;       /* PCMCIA Option Register               */
    uint32  PBR6;       /* PCMCIA Base Register                 */
    uint32  POR6;       /* PCMCIA Option Register               */
    uint32  PBR7;       /* PCMCIA Base Register                 */
    uint32  POR7;       /* PCMCIA Option Register               */
    uint32  reserved1[(1+0x0df-0x0c0)/4];
    uint32  PGCRA;      /* PCMCIA Slot A Control                */
    uint32  PGCRB;      /* PCMCIA Slot B Control                */
    uint32  PSCR;       /* PCMCIA Status Register               */
    uint32  reserved2;
    uint32  PIPR;       /* PCMCIA Pins Value Register           */
    uint32  reserved3;
    uint32  PER;        /* PCMCIA Enable                        */
    uint32  reserved4;
} MPC8XX_PCMCIA;

/* FIX !!! missing PBR macros */

#define MPC8XX_PCMCIA_POR_BSIZE_1BYTES      (0x00000000)
#define MPC8XX_PCMCIA_POR_BSIZE_2BYTES      (0x08000000)
#define MPC8XX_PCMCIA_POR_BSIZE_4BYTES      (0x18000000)
#define MPC8XX_PCMCIA_POR_BSIZE_8BYTES      (0x10000000)
#define MPC8XX_PCMCIA_POR_BSIZE_16BYTES     (0x30000000)
#define MPC8XX_PCMCIA_POR_BSIZE_32BYTES     (0x38000000)
#define MPC8XX_PCMCIA_POR_BSIZE_64BYTES     (0x28000000)
#define MPC8XX_PCMCIA_POR_BSIZE_128BYTES    (0x20000000)
#define MPC8XX_PCMCIA_POR_BSIZE_256BYTES    (0x60000000)
#define MPC8XX_PCMCIA_POR_BSIZE_512BYTES    (0x68000000)
#define MPC8XX_PCMCIA_POR_BSIZE_1024BYTES   (0x78000000)
#define MPC8XX_PCMCIA_POR_BSIZE_1K          (0x78000000)
#define MPC8XX_PCMCIA_POR_BSIZE_2K          (0x70000000)
#define MPC8XX_PCMCIA_POR_BSIZE_4K          (0x50000000)
#define MPC8XX_PCMCIA_POR_BSIZE_8K          (0x58000000)
#define MPC8XX_PCMCIA_POR_BSIZE_16K         (0x48000000)
#define MPC8XX_PCMCIA_POR_BSIZE_32K         (0x40000000)
#define MPC8XX_PCMCIA_POR_BSIZE_64K         (0xC0000000)
#define MPC8XX_PCMCIA_POR_BSIZE_128K        (0xC8000000)
#define MPC8XX_PCMCIA_POR_BSIZE_256K        (0xD8000000)
#define MPC8XX_PCMCIA_POR_BSIZE_512K        (0xD0000000)
#define MPC8XX_PCMCIA_POR_BSIZE_1024K       (0xF0000000)
#define MPC8XX_PCMCIA_POR_BSIZE_1M          (0xF0000000)
#define MPC8XX_PCMCIA_POR_BSIZE_2M          (0xF8000000)

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