📄 mcf5204.h
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#define MCF5204_SIM_PADDR_PA7_INPUT (~0x80)
#define MCF5204_SIM_PADDR_PA7_OUTPUT ( 0x80)
#define MCF5204_SIM_PADDR_PA6 ( 0x40)
#define MCF5204_SIM_PADDR_PA6_INPUT (~0x40)
#define MCF5204_SIM_PADDR_PA6_OUTPUT ( 0x40)
#define MCF5204_SIM_PADDR_PA5 ( 0x20)
#define MCF5204_SIM_PADDR_PA5_INPUT (~0x20)
#define MCF5204_SIM_PADDR_PA5_OUTPUT ( 0x20)
#define MCF5204_SIM_PADDR_PA4 ( 0x10)
#define MCF5204_SIM_PADDR_PA4_INPUT (~0x10)
#define MCF5204_SIM_PADDR_PA4_OUTPUT ( 0x10)
#define MCF5204_SIM_PADDR_PA3 ( 0x08)
#define MCF5204_SIM_PADDR_PA3_INPUT (~0x08)
#define MCF5204_SIM_PADDR_PA3_OUTPUT ( 0x08)
#define MCF5204_SIM_PADDR_PA2 ( 0x04)
#define MCF5204_SIM_PADDR_PA2_INPUT (~0x04)
#define MCF5204_SIM_PADDR_PA2_OUTPUT ( 0x04)
#define MCF5204_SIM_PADDR_PA1 ( 0x02)
#define MCF5204_SIM_PADDR_PA1_INPUT (~0x02)
#define MCF5204_SIM_PADDR_PA1_OUTPUT ( 0x02)
#define MCF5204_SIM_PADDR_PA0 ( 0x01)
#define MCF5204_SIM_PADDR_PA0_INPUT (~0x01)
#define MCF5204_SIM_PADDR_PA0_OUTPUT ( 0x01)
#define MCF5204_SIM_PADAT_PA7 ( 0x80)
#define MCF5204_SIM_PADAT_PA6 ( 0x40)
#define MCF5204_SIM_PADAT_PA5 ( 0x20)
#define MCF5204_SIM_PADAT_PA4 ( 0x10)
#define MCF5204_SIM_PADAT_PA3 ( 0x08)
#define MCF5204_SIM_PADAT_PA2 ( 0x04)
#define MCF5204_SIM_PADAT_PA1 ( 0x02)
#define MCF5204_SIM_PADAT_PA0 ( 0x01)
#define MCF5204_SIM_CSAR_BASE(a) ((a)&0xFFFFFE00)
#define MCF5204_SIM_CSMR_MASK_4M (0x003FFE00)
#define MCF5204_SIM_CSMR_MASK_2M (0x001FFE00)
#define MCF5204_SIM_CSMR_MASK_1M (0x000FFE00)
#define MCF5204_SIM_CSMR_MASK_1024K (0x000FFE00)
#define MCF5204_SIM_CSMR_MASK_512K (0x0007FE00)
#define MCF5204_SIM_CSMR_MASK_256K (0x0003FE00)
#define MCF5204_SIM_CSMR_MASK_128K (0x0001FE00)
#define MCF5204_SIM_CSMR_MASK_64K (0x0000FE00)
#define MCF5204_SIM_CSMR_MASK_32K (0x00007E00)
#define MCF5204_SIM_CSMR_MASK_16K (0x00003E00)
#define MCF5204_SIM_CSMR_MASK_8K (0x00001E00)
#define MCF5204_SIM_CSMR_MASK_4K (0x00000E00)
#define MCF5204_SIM_CSMR_MASK_2K (0x00000600)
#define MCF5204_SIM_CSMR_MASK_1K (0x00000200)
#define MCF5204_SIM_CSMR_MASK_512B (0x00000000)
#define MCF5204_SIM_CSMR_WP (0x00000100)
#define MCF5204_SIM_CSMR_CI (0x00000020)
#define MCF5204_SIM_CSMR_SC (0x00000010)
#define MCF5204_SIM_CSMR_SD (0x00000008)
#define MCF5204_SIM_CSMR_UC (0x00000004)
#define MCF5204_SIM_CSMR_UD (0x00000002)
#define MCF5204_SIM_CSCR_WS_MASK (0x00001C00)
#define MCF5204_SIM_CSCR_WS(a) (((a)&0x07)<<10)
#define MCF5204_SIM_CSCR_WS_0 (0x00000000)
#define MCF5204_SIM_CSCR_WS_1 (0x00000400)
#define MCF5204_SIM_CSCR_WS_2 (0x00000800)
#define MCF5204_SIM_CSCR_WS_3 (0x00000C00)
#define MCF5204_SIM_CSCR_WS_4 (0x00001000)
#define MCF5204_SIM_CSCR_WS_5 (0x00001400)
#define MCF5204_SIM_CSCR_WS_6 (0x00001800)
#define MCF5204_SIM_CSCR_WS_7 (0x00001C00)
#define MCF5204_SIM_CSCR_BRST (0x00000200)
#define MCF5204_SIM_CSCR_AA (0x00000100)
#define MCF5204_SIM_CSCR_PS_8 (0x00000040)
#define MCF5204_SIM_CSCR_PS_16 (0x00000000)
#define MCF5204_SIM_CSCR_BEM (0x00000020)
#define MCF5204_SIM_CSCR_V (0x00000001)
#define MCF5204_IACK_ADDRESS (0xFFFFFFE0)
#define MCF5204_IACK_MASK (MCF5204_SIM_CSMR_MASK_512B)
/***********************************************************************/
/*
* Timer Module, TIMER
*/
/* Offsets of the registers from the MBAR */
#define MCF5204_TIMER_TMR1 (0x100)
#define MCF5204_TIMER_TRR1 (0x104)
#define MCF5204_TIMER_TCR1 (0x108)
#define MCF5204_TIMER_TCN1 (0x10C)
#define MCF5204_TIMER_TER1 (0x111)
#define MCF5204_TIMER_TMR2 (0x120)
#define MCF5204_TIMER_TRR2 (0x124)
#define MCF5204_TIMER_TCR2 (0x128)
#define MCF5204_TIMER_TCN2 (0x12C)
#define MCF5204_TIMER_TER2 (0x131)
/* Read access macros for general use */
#define MCF5204_RD_TIMER_TMR1(IMMP) Mcf5204_iord(IMMP,MCF5204_TIMER_TMR1,16)
#define MCF5204_RD_TIMER_TRR1(IMMP) Mcf5204_iord(IMMP,MCF5204_TIMER_TRR1,16)
#define MCF5204_RD_TIMER_TCR1(IMMP) Mcf5204_iord(IMMP,MCF5204_TIMER_TCR1,16)
#define MCF5204_RD_TIMER_TCN1(IMMP) Mcf5204_iord(IMMP,MCF5204_TIMER_TCN1,16)
#define MCF5204_RD_TIMER_TER1(IMMP) Mcf5204_iord(IMMP,MCF5204_TIMER_TER1,16)
#define MCF5204_RD_TIMER_TMR2(IMMP) Mcf5204_iord(IMMP,MCF5204_TIMER_TMR2,16)
#define MCF5204_RD_TIMER_TRR2(IMMP) Mcf5204_iord(IMMP,MCF5204_TIMER_TRR2,16)
#define MCF5204_RD_TIMER_TCR2(IMMP) Mcf5204_iord(IMMP,MCF5204_TIMER_TCR2,16)
#define MCF5204_RD_TIMER_TCN2(IMMP) Mcf5204_iord(IMMP,MCF5204_TIMER_TCN2,16)
#define MCF5204_RD_TIMER_TER2(IMMP) Mcf5204_iord(IMMP,MCF5204_TIMER_TER2,16)
/* Write access macros for general use */
#define MCF5204_WR_TIMER_TMR1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_TIMER_TMR1,16,DATA)
#define MCF5204_WR_TIMER_TRR1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_TIMER_TRR1,16,DATA)
#define MCF5204_WR_TIMER_TCR1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_TIMER_TCR1,16,DATA)
#define MCF5204_WR_TIMER_TCN1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_TIMER_TCN1,16,DATA)
#define MCF5204_WR_TIMER_TER1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_TIMER_TER1,16,DATA)
#define MCF5204_WR_TIMER_TMR2(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_TIMER_TMR2,16,DATA)
#define MCF5204_WR_TIMER_TRR2(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_TIMER_TRR2,16,DATA)
#define MCF5204_WR_TIMER_TCR2(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_TIMER_TCR2,16,DATA)
#define MCF5204_WR_TIMER_TCN2(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_TIMER_TCN2,16,DATA)
#define MCF5204_WR_TIMER_TER2(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_TIMER_TER2,16,DATA)
#if 0
typedef volatile struct
{
uint32 reserved1[64];
uint16 TMR1;
uint16 reserved2;
uint16 TRR1;
uint16 reserved3;
uint16 TCR1;
uint16 reserved4;
uint16 TCN1;
uint16 reserved5;
uint8 reserved6;
uint8 TER1;
uint16 reserved7;
uint32 reserved8;
uint32 reserved9;
uint32 reserved10;
uint16 TMR2;
uint16 reserved11;
uint16 TRR2;
uint16 reserved12;
uint16 TCR2;
uint16 reserved13;
uint16 TCN2;
uint16 reserved14;
uint8 reserved15;
uint8 TER2;
uint16 reserved16;
} MCF5204_TIMER;
#endif
#define MCF5204_TIMER_TMR_PS(a) (((a)&0x00FF)<<8)
#define MCF5204_TIMER_TMR_CE (0x00C0)
#define MCF5204_TIMER_TMR_CE_ANY (0x00C0)
#define MCF5204_TIMER_TMR_CE_RISE (0x0080)
#define MCF5204_TIMER_TMR_CE_FALL (0x0040)
#define MCF5204_TIMER_TMR_CE_NONE (0x0000)
#define MCF5204_TIMER_TMR_OM (0x0020)
#define MCF5204_TIMER_TMR_ORI (0x0010)
#define MCF5204_TIMER_TMR_FRR (0x0008)
#define MCF5204_TIMER_TMR_CLK (0x0006)
#define MCF5204_TIMER_TMR_CLK_TIN (0x0006)
#define MCF5204_TIMER_TMR_CLK_DIV16 (0x0004)
#define MCF5204_TIMER_TMR_CLK_MSCLK (0x0002)
#define MCF5204_TIMER_TMR_CLK_STOP (0x0000)
#define MCF5204_TIMER_TMR_RST (0x0001)
#define MCF5204_TIMER_TER_REF (0x02)
#define MCF5204_TIMER_TER_CAP (0x01)
/***********************************************************************/
/*
* UART Module, UART
*/
#define MCF5204_UART_UMR (0x140)
#define MCF5204_UART_USR (0x144)
#define MCF5204_UART_UCSR (0x144)
#define MCF5204_UART_UCR (0x148)
#define MCF5204_UART_URB (0x14C)
#define MCF5204_UART_UTB (0x14C)
#define MCF5204_UART_UIPCR (0x150)
#define MCF5204_UART_UACR (0x150)
#define MCF5204_UART_UISR (0x154)
#define MCF5204_UART_UIMR (0x154)
#define MCF5204_UART_UBG1 (0x158)
#define MCF5204_UART_UBG2 (0x15C)
#define MCF5204_UART_UIVR (0x170)
#define MCF5204_UART_UIP (0x174)
#define MCF5204_UART_UOP1 (0x178)
#define MCF5204_UART_UOP0 (0x17C)
/* Read access macros for general use */
#define MCF5204_RD_UART_UMR(IMMP) Mcf5204_iord(IMMP,MCF5204_UART_UMR,8)
#define MCF5204_RD_UART_USR(IMMP) Mcf5204_iord(IMMP,MCF5204_UART_USR,8)
#define MCF5204_RD_UART_URB(IMMP) Mcf5204_iord(IMMP,MCF5204_UART_URB,8)
#define MCF5204_RD_UART_UIPCR(IMMP) Mcf5204_iord(IMMP,MCF5204_UART_UIPCR,8)
#define MCF5204_RD_UART_UISR(IMMP) Mcf5204_iord(IMMP,MCF5204_UART_UISR,8)
#define MCF5204_RD_UART_UIVR(IMMP) Mcf5204_iord(IMMP,MCF5204_UART_UIVR,8)
#define MCF5204_RD_UART_UIP(IMMP) Mcf5204_iord(IMMP,MCF5204_UART_UIP,8)
/* Write access macros for general use */
#define MCF5204_WR_UART_UMR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_UART_UMR,8,DATA)
#define MCF5204_WR_UART_UCSR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_UART_UCSR,8,DATA)
#define MCF5204_WR_UART_UCR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_UART_UCR,8,DATA)
#define MCF5204_WR_UART_UTB(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_UART_UTB,8,DATA)
#define MCF5204_WR_UART_UACR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_UART_UACR,8,DATA)
#define MCF5204_WR_UART_UIMR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_UART_UIMR,8,DATA)
#define MCF5204_WR_UART_UBG1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_UART_UBG1,8,DATA)
#define MCF5204_WR_UART_UBG2(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_UART_UBG2,8,DATA)
#define MCF5204_WR_UART_UIVR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_UART_UIVR,8,DATA)
#define MCF5204_WR_UART_UOP1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_UART_UOP1,8,DATA)
#define MCF5204_WR_UART_UOP0(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_UART_UOP0,8,DATA)
#if 0
typedef volatile struct
{
uint32 reserved1[80];
uint8 UMR;
uint8 reserved2;
uint8 reserved3;
uint8 reserved4;
uint8 USR;
uint8 reserved5;
uint8 reserved6;
uint8 reserved7;
uint8 UCR;
uint8 reserved8;
uint8 reserved9;
uint8 reserved10;
uint8 UBUF;
uint8 reserved11;
uint8 reserved12;
uint8 reserved13;
uint8 UACR;
uint8 reserved14;
uint8 reserved15;
uint8 reserved16;
uint8 UIR;
uint8 reserved17;
uint8 reserved18;
uint8 reserved19;
uint8 UBG1;
uint8 reserved20;
uint8 reserved21;
uint8 reserved22;
uint8 UBG2;
uint32 reserved23[4];
uint8 UIVR;
uint8 reserved24;
uint8 reserved25;
uint8 reserved26;
uint8 UIP;
uint8 reserved27;
uint8 reserved28;
uint8 reserved29;
uint8 UOP1;
uint8 reserved30;
uint8 reserved31;
uint8 reserved32;
uint8 UOP0;
} MCF5204_UART;
#endif
#define MCF5204_UART_UMR1_RXRTS (0x80)
#define MCF5204_UART_UMR1_RXIRQ (0x40)
#define MCF5204_UART_UMR1_ERR (0x20)
#define MCF5204_UART_UMR1_PM (0x1C)
#define MCF5204_UART_UMR1_PM_MULTI_ADDR (0x1C)
#define MCF5204_UART_UMR1_PM_MULTI_DATA (0x18)
#define MCF5204_UART_UMR1_PM_NONE (0x10)
#define MCF5204_UART_UMR1_PM_FORCE_HI (0x0C)
#define MCF5204_UART_UMR1_PM_FORCE_LO (0x08)
#define MCF5204_UART_UMR1_PM_ODD (0x04)
#define MCF5204_UART_UMR1_PM_EVEN (0x00)
#define MCF5204_UART_UMR1_BC (0x03)
#define MCF5204_UART_UMR1_BC_5 (0x00)
#define MCF5204_UART_UMR1_BC_6 (0x01)
#define MCF5204_UART_UMR1_BC_7 (0x02)
#define MCF5204_UART_UMR1_BC_8 (0x03)
#define MCF5204_UART_UMR2_CM (0xC0)
#define MCF5204_UART_UMR2_CM_NORMAL (0x00)
#define MCF5204_UART_UMR2_CM_ECHO (0x40)
#define MCF5204_UART_UMR2_CM_LOCAL_LOOP (0x80)
#define MCF5204_UART_UMR2_CM_REMOTE_LOOP (0xC0)
#define MCF5204_UART_UMR2_TXRTS (0x20)
#define MCF5204_UART_UMR2_TXCTS (0x10)
#define MCF5204_UART_UMR2_STOP_BITS (0x0F)
#define MCF5204_UART_UMR2_STOP_BITS_1 (0x07)
#define MCF5204_UART_UMR2_STOP_BITS_15 (0x08)
#define MCF5204_UART_UMR2_STOP_BITS_2 (0x0F)
#define MCF5204_UART_USR_RB (0x80)
#define MCF5204_UART_USR_FE (0x40)
#define MCF5204_UART_USR_PE (0x20)
#define MCF5204_UART_USR_OE (0x10)
#define MCF5204_UART_USR_TXEMP (0x08)
#define MCF5204_UART_USR_TXRDY (0x04)
#define MCF5204_UART_USR_FFULL (0x02)
#define MCF5204_UART_USR_RXRDY (0x01)
#define MCF5204_UART_UCSR_9600_BPS (0xBB)
#define MCF5204_UART_UCSR_19200_BPS (0xCC)
#define MCF5204_UART_UCR_NONE (0x00)
#define MCF5204_UART_UCR_STOP_BREAK (0x70)
#define MCF5204_UART_UCR_START_BREAK (0x60)
#define MCF5204_UART_UCR_RESET_BKCHGINT (0x50)
#define MCF5204_UART_UCR_RESET_ERROR (0x40)
#define MCF5204_UART_UCR_RESET_TX (0x30)
#define MCF5204_UART_UCR_RESET_RX (0x20)
#define MCF5204_UART_UCR_RESET_MR (0x10)
#define MCF5204_UART_UCR_TX_DISABLED (0x08)
#define MCF5204_UART_UCR_TX_ENABLED (0x04)
#define MCF5204_UART_UCR_RX_DISABLED (0x02)
#define MCF5204_UART_UCR_RX_ENABLED (0x01)
#define MCF5204_UART_UIPCR_COS (0x10)
#define MCF5204_UART_UIPCR_CTS (0x01)
#define MCF5204_UART_UACR_BRG (0x80)
#define MCF5204_UART_UACR_CTMS_TIMER (0x60)
#define MCF5204_UART_UACR_IEC (0x01)
#define MCF5204_UART_UISR_COS (0x80)
#define MCF5204_UART_UISR_DB (0x04)
#define MCF5204_UART_UISR_RXRDY (0x02)
#define MCF5204_UART_UISR_TXRDY (0x01)
#define MCF5204_UART_UIMR_COS (0x80)
#define MCF5204_UART_UIMR_DB (0x04)
#define MCF5204_UART_UIMR_FFULL (0x02)
#define MCF5204_UART_UIMR_TXRDY (0x01)
/***********************************************************************/
#if 0
/*
* Put the modules together to overlay the internal peripherals.
* Assuming compiler keeps data structures in the exact order
* provided above, an example acess to the UMR register in the
* UART is:
*
* immp->uart.UMR
*
* where 'immp' is a pointer to the internal peripherals, MCF5204_IMM *
*/
typedef volatile union
{
MCF5204_SIM sim;
MCF5204_UART uart;
MCF5204_TIMER timer;
} MCF5204_IMM;
#endif
/***********************************************************************/
#endif /* _CPU_MCF5204_H */
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