📄 mcf5204.h
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/*
* File: src/include/cpu/coldfire/mcf5204.h
* Purpose: MCF5204 definitions
*
* Notes: This file automatically included.
*
*
* Modifications:
*
*/
#ifndef _CPU_MCF5204_H
#define _CPU_MCF5204_H
/***********************************************************************/
/*
* Cache and Access Control Register routines and defintions
*/
#define MCF5204_CACR_CENB (0x80000000)
#define MCF5204_CACR_CFRZ (0x08000000)
#define MCF5204_CACR_CINV (0x01000000)
#define MCF5204_CACR_CMOD (0x00000200)
#define MCF5204_CACR_CWRP (0x00000020)
#define MCF5204_CACR_CLNF (0x00000003)
#define MCF5204_CACR_CLNF_00 (0x00000000)
#define MCF5204_CACR_CLNF_01 (0x00000001)
#define MCF5204_CACR_CLNF_10 (0x00000002)
#define MCF5204_ACR_BASE(a) ((a)&0xFF000000)
#define MCF5204_ACR_MASK(a) (((a)&0xFF000000) >> 8)
#define MCF5204_ACR_EN (0x00008000)
#define MCF5204_ACR_S_USER (0x00000000)
#define MCF5204_ACR_S_SUPER (0x00002000)
#define MCF5204_ACR_S_IGNORE (0x00006000)
#define MCF5204_ACR_ENIB (0x00000080)
#define MCF5204_ACR_CM (0x00000040)
#define MCF5204_ACR_WP (0x00000004)
#define MCF5204_SRAMBAR_BASE(a) ((a)&0xFFFFFE00)
#define MCF5204_SRAMBAR_WP (0x00000100)
#define MCF5204_SRAMBAR_AS_CI (0x00000080)
#define MCF5204_SRAMBAR_AS_SC (0x00000040)
#define MCF5204_SRAMBAR_AS_SD (0x00000020)
#define MCF5204_SRAMBAR_AS_UC (0x00000004)
#define MCF5204_SRAMBAR_AS_UD (0x00000002)
#define MCF5204_SRAMBAR_V (0x00000001)
#define MCF5204_MBAR_BASE(a) ((a)&0xFFFFFE00)
#define MCF5204_MBAR_CI (0x00000020)
#define MCF5204_MBAR_SC (0x00000010)
#define MCF5204_MBAR_SD (0x00000008)
#define MCF5204_MBAR_UC (0x00000004)
#define MCF5204_MBAR_UD (0x00000002)
#define MCF5204_MBAR_V (0x00000001)
/***********************************************************************/
/*
* Macro for computing address of on-chip peripheral registers
*/
#define Mcf5204_addr(IMMP,OFFSET) ((void *)&((uint8 *)IMMP)[OFFSET])
/*
* Macros for accessing the on-chip I/O resources
*/
#define Mcf5204_iord(IMMP,OFFSET,SIZE) \
*(volatile uint ## SIZE *)(Mcf5204_addr(IMMP,OFFSET))
#define Mcf5204_iowr(IMMP,OFFSET,SIZE,DATA) \
*(volatile uint ## SIZE *)(Mcf5204_addr(IMMP,OFFSET)) = (DATA)
/***********************************************************************/
/*
* System Integration Modules, SIM
*/
/* Offsets of the registers from the MBAR */
#define MCF5204_SIM_SIMR (0x003)
#define MCF5204_SIM_ICR_E0 (0x014)
#define MCF5204_SIM_ICR_E1 (0x015)
#define MCF5204_SIM_ICR_E2 (0x016)
#define MCF5204_SIM_ICR_E3 (0x017)
#define MCF5204_SIM_ICR_SW (0x01B)
#define MCF5204_SIM_ICR_T1 (0x01C)
#define MCF5204_SIM_ICR_T2 (0x01D)
#define MCF5204_SIM_ICR_U1 (0x01F)
#define MCF5204_SIM_IMR (0x034)
#define MCF5204_SIM_IPR (0x038)
#define MCF5204_SIM_RSR (0x040)
#define MCF5204_SIM_SYPCR (0x041)
#define MCF5204_SIM_SWIVR (0x042)
#define MCF5204_SIM_SWSR (0x043)
#define MCF5204_SIM_CSAR0 (0x064)
#define MCF5204_SIM_CSMR0 (0x068)
#define MCF5204_SIM_CSCR0 (0x06C)
#define MCF5204_SIM_CSAR1 (0x070)
#define MCF5204_SIM_CSMR1 (0x074)
#define MCF5204_SIM_CSCR1 (0x078)
#define MCF5204_SIM_CSAR2 (0x07C)
#define MCF5204_SIM_CSMR2 (0x080)
#define MCF5204_SIM_CSCR2 (0x084)
#define MCF5204_SIM_CSAR3 (0x088)
#define MCF5204_SIM_CSMR3 (0x08C)
#define MCF5204_SIM_CSCR3 (0x090)
#define MCF5204_SIM_CSAR4 (0x094)
#define MCF5204_SIM_CSMR4 (0x098)
#define MCF5204_SIM_CSCR4 (0x09C)
#define MCF5204_SIM_CSAR5 (0x0A0)
#define MCF5204_SIM_CSMR5 (0x0A4)
#define MCF5204_SIM_CSCR5 (0x0A8)
#define MCF5204_SIM_PAR (0x0CB)
#define MCF5204_SIM_PADDR (0x1C5)
#define MCF5204_SIM_PADAT (0x1C9)
/* Read access macros for general use */
#define MCF5204_RD_SIM_SIMR(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_SIMR,8)
#define MCF5204_RD_SIM_ICR_E0(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_ICR_E0,8)
#define MCF5204_RD_SIM_ICR_E1(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_ICR_E1,8)
#define MCF5204_RD_SIM_ICR_E2(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_ICR_E2,8)
#define MCF5204_RD_SIM_ICR_E3(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_ICR_E3,8)
#define MCF5204_RD_SIM_ICR_SW(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_ICR_SW,8)
#define MCF5204_RD_SIM_ICR_T1(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_ICR_T1,8)
#define MCF5204_RD_SIM_ICR_T2(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_ICR_T2,8)
#define MCF5204_RD_SIM_ICR_U1(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_ICR_U1,8)
#define MCF5204_RD_SIM_IMR(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_IMR,32)
#define MCF5204_RD_SIM_IPR(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_IPR,32)
#define MCF5204_RD_SIM_RSR(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_RSR,8)
#define MCF5204_RD_SIM_SYPCR(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_SYPCR,8)
#define MCF5204_RD_SIM_SWIVR(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_SWIVR,8)
#define MCF5204_RD_SIM_SWSR(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_SWSR,8)
#define MCF5204_RD_SIM_CSAR0(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSAR0,32)
#define MCF5204_RD_SIM_CSMR0(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSMR0,32)
#define MCF5204_RD_SIM_CSCR0(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSCR0,32)
#define MCF5204_RD_SIM_CSAR1(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSAR1,32)
#define MCF5204_RD_SIM_CSMR1(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSMR1,32)
#define MCF5204_RD_SIM_CSCR1(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSCR1,32)
#define MCF5204_RD_SIM_CSAR2(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSAR2,32)
#define MCF5204_RD_SIM_CSMR2(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSMR2,32)
#define MCF5204_RD_SIM_CSCR2(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSCR2,32)
#define MCF5204_RD_SIM_CSAR3(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSAR3,32)
#define MCF5204_RD_SIM_CSMR3(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSMR3,32)
#define MCF5204_RD_SIM_CSCR3(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSCR3,32)
#define MCF5204_RD_SIM_CSAR4(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSAR4,32)
#define MCF5204_RD_SIM_CSMR4(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSMR4,32)
#define MCF5204_RD_SIM_CSCR4(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSCR4,32)
#define MCF5204_RD_SIM_CSAR5(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSAR5,32)
#define MCF5204_RD_SIM_CSMR5(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSMR5,32)
#define MCF5204_RD_SIM_CSCR5(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_CSCR5,32)
#define MCF5204_RD_SIM_PAR(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_PAR,8)
#define MCF5204_RD_SIM_PADDR(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_PADDR,8)
#define MCF5204_RD_SIM_PADAT(IMMP) Mcf5204_iord(IMMP,MCF5204_SIM_PADAT,8)
/* Write access macros for general use */
#define MCF5204_WR_SIM_SIMR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_SIMR,8,DATA)
#define MCF5204_WR_SIM_ICR_E0(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_ICR_E0,8,DATA)
#define MCF5204_WR_SIM_ICR_E1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_ICR_E1,8,DATA)
#define MCF5204_WR_SIM_ICR_E2(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_ICR_E2,8,DATA)
#define MCF5204_WR_SIM_ICR_E3(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_ICR_E3,8,DATA)
#define MCF5204_WR_SIM_ICR_SW(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_ICR_SW,8,DATA)
#define MCF5204_WR_SIM_ICR_T1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_ICR_T1,8,DATA)
#define MCF5204_WR_SIM_ICR_T2(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_ICR_T2,8,DATA)
#define MCF5204_WR_SIM_ICR_U1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_ICR_U1,8,DATA)
#define MCF5204_WR_SIM_IMR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_IMR,32,DATA)
#define MCF5204_WR_SIM_IPR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_IPR,32,DATA)
#define MCF5204_WR_SIM_RSR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_RSR,8,DATA)
#define MCF5204_WR_SIM_SYPCR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_SYPCR,8,DATA)
#define MCF5204_WR_SIM_SWIVR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_SWIVR,8,DATA)
#define MCF5204_WR_SIM_SWSR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_SWSR,8,DATA)
#define MCF5204_WR_SIM_CSAR0(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSAR0,32,DATA)
#define MCF5204_WR_SIM_CSMR0(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSMR0,32,DATA)
#define MCF5204_WR_SIM_CSCR0(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSCR0,32,DATA)
#define MCF5204_WR_SIM_CSAR1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSAR1,32,DATA)
#define MCF5204_WR_SIM_CSMR1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSMR1,32,DATA)
#define MCF5204_WR_SIM_CSCR1(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSCR1,32,DATA)
#define MCF5204_WR_SIM_CSAR2(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSAR2,32,DATA)
#define MCF5204_WR_SIM_CSMR2(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSMR2,32,DATA)
#define MCF5204_WR_SIM_CSCR2(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSCR2,32,DATA)
#define MCF5204_WR_SIM_CSAR3(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSAR3,32,DATA)
#define MCF5204_WR_SIM_CSMR3(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSMR3,32,DATA)
#define MCF5204_WR_SIM_CSCR3(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSCR3,32,DATA)
#define MCF5204_WR_SIM_CSAR4(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSAR4,32,DATA)
#define MCF5204_WR_SIM_CSMR4(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSMR4,32,DATA)
#define MCF5204_WR_SIM_CSCR4(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSCR4,32,DATA)
#define MCF5204_WR_SIM_CSAR5(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSAR5,32,DATA)
#define MCF5204_WR_SIM_CSMR5(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSMR5,32,DATA)
#define MCF5204_WR_SIM_CSCR5(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_CSCR5,32,DATA)
#define MCF5204_WR_SIM_PAR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_PAR,8,DATA)
#define MCF5204_WR_SIM_PADDR(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_PADDR,8,DATA)
#define MCF5204_WR_SIM_PADAT(IMMP,DATA) \
Mcf5204_iowr(IMMP,MCF5204_SIM_PADAT,8,DATA)
#if 0
typedef volatile struct
{
uint8 reserved0;
uint8 reserved1;
uint8 reserved2;
uint8 SIMR;
uint32 reserved3;
uint32 reserved4;
uint32 reserved5;
uint32 reserved6;
uint8 ICR_E0;
uint8 ICR_E1;
uint8 ICR_E2;
uint8 ICR_E3;
uint8 reserved7;
uint8 reserved8;
uint8 reserved9;
uint8 ICR_SW;
uint8 ICR_T1;
uint8 ICR_T2;
uint8 reserved10;
uint8 ICR_U1;
uint32 reserved11;
uint32 reserved12[4];
uint32 IMR;
uint32 IPR;
uint32 reserved13;
uint8 RSR;
uint8 SYPCR;
uint8 SWIVR;
uint8 SWSR;
uint32 reserved14;
uint32 reserved15;
uint32 reserved16;
uint32 reserved17;
uint32 reserved18;
uint32 reserved19;
uint32 reserved20;
uint32 reserved21;
uint32 CSAR0;
uint32 CSMR0;
uint32 CSCR0;
uint32 CSAR1;
uint32 CSMR1;
uint32 CSCR1;
uint32 CSAR2;
uint32 CSMR2;
uint32 CSCR2;
uint32 CSAR3;
uint32 CSMR3;
uint32 CSCR3;
uint32 CSAR4;
uint32 CSMR4;
uint32 CSCR4;
uint32 CSAR5;
uint32 CSMR5;
uint32 CSCR5;
uint32 reserved22;
uint32 reserved23;
uint32 reserved24;
uint32 reserved25;
uint32 reserved26;
uint32 reserved27;
uint32 reserved28;
uint8 reserved29;
uint8 reserved30;
uint8 reserved31;
uint8 PAR;
uint32 reserved32[62];
uint8 reserved33;
uint8 PADDR;
uint8 reserved34;
uint8 reserved35;
uint8 reserved36;
uint8 PADAT;
} MCF5204_SIM;
#endif
#define MCF5204_SIM_SIMR_FRZ1 (0x80)
#define MCF5204_SIM_SIMR_FRZ0 (0x40)
#define MCF5204_SIM_ICR_AVEC (0x80)
#define MCF5204_SIM_ICR_IL(a) (((a)&0x07)<<2)
#define MCF5204_SIM_ICR_IP(a) (((a)&0x03))
#define MCF5204_SIM_IMR_UART (0x00001000)
#define MCF5204_SIM_IMR_T2 (0x00000400)
#define MCF5204_SIM_IMR_T1 (0x00000200)
#define MCF5204_SIM_IMR_SWT (0x00000100)
#define MCF5204_SIM_IMR_IRQ3 (0x00000010)
#define MCF5204_SIM_IMR_IRQ2 (0x00000008)
#define MCF5204_SIM_IMR_IRQ1 (0x00000004)
#define MCF5204_SIM_IMR_IRQ0 (0x00000002)
#define MCF5204_SIM_IPR_UART (0x00001000)
#define MCF5204_SIM_IPR_T2 (0x00000400)
#define MCF5204_SIM_IPR_T1 (0x00000200)
#define MCF5204_SIM_IPR_SWT (0x00000100)
#define MCF5204_SIM_IPR_IRQ3 (0x00000010)
#define MCF5204_SIM_IPR_IRQ2 (0x00000008)
#define MCF5204_SIM_IPR_IRQ1 (0x00000004)
#define MCF5204_SIM_IPR_IRQ0 (0x00000002)
#define MCF5204_SIM_RSR_HRST (0x80)
#define MCF5204_SIM_RSR_SWTR (0x20)
#define MCF5204_SIM_SYPCR_SWE (0x80)
#define MCF5204_SIM_SYPCR_SWRI (0x40)
#define MCF5204_SIM_SYPCR_SWT (0x38)
#define MCF5204_SIM_SYPCR_SWT_2_9 (0x00)
#define MCF5204_SIM_SYPCR_SWT_2_11 (0x08)
#define MCF5204_SIM_SYPCR_SWT_2_13 (0x10)
#define MCF5204_SIM_SYPCR_SWT_2_15 (0x18)
#define MCF5204_SIM_SYPCR_SWT_2_18 (0x20)
#define MCF5204_SIM_SYPCR_SWT_2_20 (0x28)
#define MCF5204_SIM_SYPCR_SWT_2_22 (0x30)
#define MCF5204_SIM_SYPCR_SWT_2_24 (0x38)
#define MCF5204_SIM_SYPCR_BME (0x04)
#define MCF5204_SIM_SYPCR_BM (0x03)
#define MCF5204_SIM_SYPCR_BM_1024 (0x00)
#define MCF5204_SIM_SYPCR_BM_512 (0x01)
#define MCF5204_SIM_SYPCR_BM_256 (0x02)
#define MCF5204_SIM_SYPCR_BM_128 (0x03)
#define MCF5204_SIM_SWIVR_SWIV(a) ((a)&0x00FF)
#define MCF5204_SIM_PAR_PAR0 ( 0x01)
#define MCF5204_SIM_PAR_PAR0_PA0 ( 0x01)
#define MCF5204_SIM_PAR_PAR0_A20 (~0x01)
#define MCF5204_SIM_PAR_PAR1 ( 0x02)
#define MCF5204_SIM_PAR_PAR1_PA1 ( 0x02)
#define MCF5204_SIM_PAR_PAR1_A21 (~0x02)
#define MCF5204_SIM_PAR_PAR2 ( 0x04)
#define MCF5204_SIM_PAR_PAR2_PA2 ( 0x04)
#define MCF5204_SIM_PAR_PAR2_TIN (~0x04)
#define MCF5204_SIM_PAR_PAR3 ( 0x08)
#define MCF5204_SIM_PAR_PAR3_PA3 ( 0x08)
#define MCF5204_SIM_PAR_PAR3_TOUT (~0x08)
#define MCF5204_SIM_PAR_PAR4 ( 0x10)
#define MCF5204_SIM_PAR_PAR4_PA4 ( 0x10)
#define MCF5204_SIM_PAR_PAR4_TXD (~0x10)
#define MCF5204_SIM_PAR_PAR5 ( 0x20)
#define MCF5204_SIM_PAR_PAR5_PA5 ( 0x20)
#define MCF5204_SIM_PAR_PAR5_RXD (~0x20)
#define MCF5204_SIM_PAR_PAR6 ( 0x40)
#define MCF5204_SIM_PAR_PAR6_PA6 ( 0x40)
#define MCF5204_SIM_PAR_PAR6_CTS (~0x40)
#define MCF5204_SIM_PAR_PAR7 ( 0x80)
#define MCF5204_SIM_PAR_PAR7_PA7 ( 0x80)
#define MCF5204_SIM_PAR_PAR7_RTS (~0x80)
#define MCF5204_SIM_PADDR_PA7 ( 0x80)
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