mcf5272.h

motorola 针对coldfire 5275 评估板的Dbug bootloader源程序

#define MCF5272_UART0_URFCSR    (*(vuint8  *)(void *)(&__MBAR[0x012C])) /* RW */
#define MCF5272_UART0_UFPD      (*(vuint8  *)(void *)(&__MBAR[0x0130])) /* RW */
#define MCF5272_UART0_UIP       (*(vuint8  *)(void *)(&__MBAR[0x0134])) /* RO */
#define MCF5272_UART0_UOP1      (*(vuint8  *)(void *)(&__MBAR[0x0138])) /* WO */
#define MCF5272_UART0_UOP0      (*(vuint8  *)(void *)(&__MBAR[0x013C])) /* WO */

#define MCF5272_UART1_UMR       (*(vuint8  *)(void *)(&__MBAR[0x0140])) /* RW */
#define MCF5272_UART1_USR       (*(vuint8  *)(void *)(&__MBAR[0x0144])) /* USR RO */
#define MCF5272_UART1_UCSR      (*(vuint8  *)(void *)(&__MBAR[0x0144])) /* UCSR WO */
#define MCF5272_UART1_UCR       (*(vuint8  *)(void *)(&__MBAR[0x0148])) /* WO */
#define MCF5272_UART1_URB       (*(vuint8  *)(void *)(&__MBAR[0x014C])) /* URB RO */
#define MCF5272_UART1_UTB       (*(vuint8  *)(void *)(&__MBAR[0x014C])) /* UTB WO */
#define MCF5272_UART1_UIPCR     (*(vuint8  *)(void *)(&__MBAR[0x0150])) /* UIPCR RO */
#define MCF5272_UART1_UACR      (*(vuint8  *)(void *)(&__MBAR[0x0150])) /* UACR WO */
#define MCF5272_UART1_UISR      (*(vuint8  *)(void *)(&__MBAR[0x0154])) /* UISR RO */
#define MCF5272_UART1_UIMR      (*(vuint8  *)(void *)(&__MBAR[0x0154])) /* UIMR WO */
#define MCF5272_UART1_UBG1      (*(vuint8  *)(void *)(&__MBAR[0x0158])) /* WO */
#define MCF5272_UART1_UBG2      (*(vuint8  *)(void *)(&__MBAR[0x015C])) /* WO */
#define MCF5272_UART1_UABR1     (*(vuint8  *)(void *)(&__MBAR[0x0160])) /* RO */
#define MCF5272_UART1_UABR2     (*(vuint8  *)(void *)(&__MBAR[0x0164])) /* RO */
#define MCF5272_UART1_UTFCSR    (*(vuint8  *)(void *)(&__MBAR[0x0168])) /* RW */
#define MCF5272_UART1_URFCSR    (*(vuint8  *)(void *)(&__MBAR[0x016C])) /* RW */
#define MCF5272_UART1_UFPD      (*(vuint8  *)(void *)(&__MBAR[0x0170])) /* RW */
#define MCF5272_UART1_UIP       (*(vuint8  *)(void *)(&__MBAR[0x0174])) /* RO */
#define MCF5272_UART1_UOP1      (*(vuint8  *)(void *)(&__MBAR[0x0178])) /* WO */
#define MCF5272_UART1_UOP0      (*(vuint8  *)(void *)(&__MBAR[0x017C])) /* WO */

/* Bit level definitions and macros */
#define MCF5272_UART_UMR1_RXRTS         (0x80)
#define MCF5272_UART_UMR1_RXIRQ         (0x40)
#define MCF5272_UART_UMR1_ERR           (0x20)
#define MCF5272_UART_UMR1_PM_MULTI_ADDR (0x1C)
#define MCF5272_UART_UMR1_PM_MULTI_DATA (0x18)
#define MCF5272_UART_UMR1_PM_NONE       (0x10)
#define MCF5272_UART_UMR1_PM_FORCE_HI   (0x0C)
#define MCF5272_UART_UMR1_PM_FORCE_LO   (0x08)
#define MCF5272_UART_UMR1_PM_ODD        (0x04)
#define MCF5272_UART_UMR1_PM_EVEN       (0x00)
#define MCF5272_UART_UMR1_BC_5          (0x00)
#define MCF5272_UART_UMR1_BC_6          (0x01)
#define MCF5272_UART_UMR1_BC_7          (0x02)
#define MCF5272_UART_UMR1_BC_8          (0x03)

#define MCF5272_UART_UMR2_CM_NORMAL     (0x00)
#define MCF5272_UART_UMR2_CM_ECHO       (0x40)
#define MCF5272_UART_UMR2_CM_LOCAL_LOOP (0x80)
#define MCF5272_UART_UMR2_CM_REMOTE_LOOP    (0xC0)
#define MCF5272_UART_UMR2_TXRTS         (0x20)
#define MCF5272_UART_UMR2_TXCTS         (0x10)
#define MCF5272_UART_UMR2_STOP_BITS_1   (0x07)
#define MCF5272_UART_UMR2_STOP_BITS_15  (0x08)
#define MCF5272_UART_UMR2_STOP_BITS_2   (0x0F)
#define MCF5272_UART_UMR2_STOP_BITS(a)   ((a)&0x0f) /* Stop Bit Length */

#define MCF5272_UART_USR_RB             (0x80)
#define MCF5272_UART_USR_FE             (0x40)
#define MCF5272_UART_USR_PE             (0x20)
#define MCF5272_UART_USR_OE             (0x10)
#define MCF5272_UART_USR_TXEMP          (0x08)
#define MCF5272_UART_USR_TXRDY          (0x04)
#define MCF5272_UART_USR_FFULL          (0x02)
#define MCF5272_UART_USR_RXRDY          (0x01)

#define MCF5272_UART_UCSR_RCS(a)    (((a)&0x0f)<<4) /* Rx Clk Select */
#define MCF5272_UART_UCSR_TCS(a)        ((a)&0x0f)  /* Tx Clk Select */


#define MCF5272_UART_UCR_NONE           (0x00)
#define MCF5272_UART_UCR_STOP_BREAK     (0x70)
#define MCF5272_UART_UCR_START_BREAK    (0x60)
#define MCF5272_UART_UCR_RESET_BKCHGINT (0x50)
#define MCF5272_UART_UCR_RESET_ERROR    (0x40)
#define MCF5272_UART_UCR_RESET_TX       (0x30)
#define MCF5272_UART_UCR_RESET_RX       (0x20)
#define MCF5272_UART_UCR_RESET_MR       (0x10)
#define MCF5272_UART_UCR_TX_DISABLED    (0x08)
#define MCF5272_UART_UCR_TX_ENABLED     (0x04)
#define MCF5272_UART_UCR_RX_DISABLED    (0x02)
#define MCF5272_UART_UCR_RX_ENABLED     (0x01)

#define MCF5272_UART_UCCR_COS           (0x10)
#define MCF5272_UART_UCCR_CTS           (0x01)

#define MCF5272_UART_UACR_BRG           (0x80)
#define MCF5272_UART_UACR_CTMS_TIMER    (0x60)
#define MCF5272_UART_UACR_IEC           (0x01)

#define MCF5272_UART_UISR_COS           (0x80)
#define MCF5272_UART_UISR_DB            (0x04)
#define MCF5272_UART_UISR_RXRDY         (0x02)
#define MCF5272_UART_UISR_TXRDY         (0x01)

#define MCF5272_UART_UIMR_COS           (0x80)
#define MCF5272_UART_UIMR_DB            (0x04)
#define MCF5272_UART_UIMR_FFULL         (0x02)
#define MCF5272_UART_UIMR_TXRDY         (0x01)


/**********************************************************************
*
* SDRAM Controller Module Registers Description
*
***********************************************************************/

/* Read/Write access macros for general use */
#define MCF5272_SDRAMC_SDCCR        (*(vuint16 *)(void *)(&__MBAR[0x0182]))
#define MCF5272_SDRAMC_SDCTR        (*(vuint16 *)(void *)(&__MBAR[0x0186]))

/* Bit level definitions and macros */
#define MCF5272_SDRAMC_SDCCR_MCAS_A7    (0x0 << 13)
#define MCF5272_SDRAMC_SDCCR_MCAS_A8    (0x1 << 13)
#define MCF5272_SDRAMC_SDCCR_MCAS_A9    (0x2 << 13)
#define MCF5272_SDRAMC_SDCCR_MCAS_A10   (0x3 << 13)
#define MCF5272_SDRAMC_SDCCR_BALOC_A19  (0x0 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A20  (0x1 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A21  (0x2 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A22  (0x3 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A23  (0x4 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A24  (0x5 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A25  (0x6 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A26  (0x7 << 8)
#define MCF5272_SDRAMC_SDCCR_GSL        (0x00000080)
#define MCF5272_SDRAMC_SDCCR_REG        (0x00000010)
#define MCF5272_SDRAMC_SDCCR_INV        (0x00000008)
#define MCF5272_SDRAMC_SDCCR_SLEEP      (0x00000004)
#define MCF5272_SDRAMC_SDCCR_ACT        (0x00000002)
#define MCF5272_SDRAMC_SDCCR_INIT       (0x00000001)

#define MCF5272_SDRAMC_SDCTR_RTP_66MHz  (0x3D << 10)
#define MCF5272_SDRAMC_SDCTR_RTP_48MHz  (0x2B << 10)
#define MCF5272_SDRAMC_SDCTR_RTP_33MHz  (0x1D << 10)
#define MCF5272_SDRAMC_SDCTR_RTP_25MHz  (0x16 << 10)
#define MCF5272_SDRAMC_SDCTR_RC(x)      ((x & 0x3) << 8)
#define MCF5272_SDRAMC_SDCTR_RP(x)      ((x & 0x3) << 4)
#define MCF5272_SDRAMC_SDCTR_RCD(x)     ((x & 0x3) << 2)
#define MCF5272_SDRAMC_SDCTR_CLT_2      (0x00000001)
#define MCF5272_SDRAMC_SDCTR_CLT_3      (0x00000002)
#define MCF5272_SDRAMC_SDCTR_CLT_4      (0x00000003)

/**********************************************************************
*
* Timer Module Registers Description
*
***********************************************************************/

/* Read/Write access macros for general use */
#define MCF5272_TIMER0_TMR      (*(vuint16 *)(void *)(&__MBAR[0x0200]))
#define MCF5272_TIMER0_TRR      (*(vuint16 *)(void *)(&__MBAR[0x0204]))
#define MCF5272_TIMER0_TCR      (*(vuint16 *)(void *)(&__MBAR[0x0208]))
#define MCF5272_TIMER0_TCN      (*(vuint16 *)(void *)(&__MBAR[0x020C]))
#define MCF5272_TIMER0_TER      (*(vuint16 *)(void *)(&__MBAR[0x0210]))
#define MCF5272_TIMER1_TMR      (*(vuint16 *)(void *)(&__MBAR[0x0220]))
#define MCF5272_TIMER1_TRR      (*(vuint16 *)(void *)(&__MBAR[0x0224]))
#define MCF5272_TIMER1_TCR      (*(vuint16 *)(void *)(&__MBAR[0x0228]))
#define MCF5272_TIMER1_TCN      (*(vuint16 *)(void *)(&__MBAR[0x022C]))
#define MCF5272_TIMER1_TER      (*(vuint16 *)(void *)(&__MBAR[0x0230]))
#define MCF5272_TIMER2_TMR      (*(vuint16 *)(void *)(&__MBAR[0x0240]))
#define MCF5272_TIMER2_TRR      (*(vuint16 *)(void *)(&__MBAR[0x0244]))
#define MCF5272_TIMER2_TCR      (*(vuint16 *)(void *)(&__MBAR[0x0248]))
#define MCF5272_TIMER2_TCN      (*(vuint16 *)(void *)(&__MBAR[0x024C]))
#define MCF5272_TIMER2_TER      (*(vuint16 *)(void *)(&__MBAR[0x0250]))
#define MCF5272_TIMER3_TMR      (*(vuint16 *)(void *)(&__MBAR[0x0260]))
#define MCF5272_TIMER3_TRR      (*(vuint16 *)(void *)(&__MBAR[0x0264]))
#define MCF5272_TIMER3_TCR      (*(vuint16 *)(void *)(&__MBAR[0x0268]))
#define MCF5272_TIMER3_TCN      (*(vuint16 *)(void *)(&__MBAR[0x026C]))
#define MCF5272_TIMER3_TER      (*(vuint16 *)(void *)(&__MBAR[0x0270]))
#define MCF5272_TIMER_WRRR      (*(vuint16 *)(void *)(&__MBAR[0x0280]))
#define MCF5272_TIMER_WIRR      (*(vuint16 *)(void *)(&__MBAR[0x0284]))
#define MCF5272_TIMER_WCR       (*(vuint16 *)(void *)(&__MBAR[0x0288]))
#define MCF5272_TIMER_WER       (*(vuint16 *)(void *)(&__MBAR[0x028C]))
#define MCF5272_TIMER_TMR(x)    (*(vuint16 *)(void *)(&__MBAR[0x0200+(x*0x20)]))
#define MCF5272_TIMER_TRR(x)    (*(vuint16 *)(void *)(&__MBAR[0x0204+(x*0x20)]))
#define MCF5272_TIMER_TCR(x)    (*(vuint16 *)(void *)(&__MBAR[0x0208+(x*0x20)]))
#define MCF5272_TIMER_TCN(x)    (*(vuint16 *)(void *)(&__MBAR[0x020C+(x*0x20)]))
#define MCF5272_TIMER_TER(x)    (*(vuint16 *)(void *)(&__MBAR[0x0210+(x*0x20)]))

/* Bit level definitions and macros */
#define MCF5272_TIMER_TMR_PS(a)     (((a)&0x00FF)<<8)
#define MCF5272_TIMER_TMR_CE_ANY    (0x00C0)
#define MCF5272_TIMER_TMR_CE_RISE   (0x0080)
#define MCF5272_TIMER_TMR_CE_FALL   (0x0040)
#define MCF5272_TIMER_TMR_CE_NONE   (0x0000)
#define MCF5272_TIMER_TMR_OM        (0x0020)
#define MCF5272_TIMER_TMR_ORI       (0x0010)
#define MCF5272_TIMER_TMR_FRR       (0x0008)
#define MCF5272_TIMER_TMR_CLK_TIN   (0x0006)
#define MCF5272_TIMER_TMR_CLK_DIV16 (0x0004)
#define MCF5272_TIMER_TMR_CLK_MSCLK (0x0002)
#define MCF5272_TIMER_TMR_CLK_STOP  (0x0000)
#define MCF5272_TIMER_TMR_RST       (0x0001)

#define MCF5272_TIMER_TER_REF       (0x02)
#define MCF5272_TIMER_TER_CAP       (0x01)

/**********************************************************************
*
* PLI Module Registers Description
*
***********************************************************************/

/* Read/Write access macros for general use */
#define MCF5272_PLI_P0B1RR          (*(vuint32 *)(void *)(&__MBAR[0x0300]))
#define MCF5272_PLI_P1B1RR          (*(vuint32 *)(void *)(&__MBAR[0x0304]))
#define MCF5272_PLI_P2B1RR          (*(vuint32 *)(void *)(&__MBAR[0x0308]))
#define MCF5272_PLI_P3B1RR          (*(vuint32 *)(void *)(&__MBAR[0x030C]))
#define MCF5272_PLI_P0B2RR          (*(vuint32 *)(void *)(&__MBAR[0x0310]))
#define MCF5272_PLI_P1B2RR          (*(vuint32 *)(void *)(&__MBAR[0x0314]))
#define MCF5272_PLI_P2B2RR          (*(vuint32 *)(void *)(&__MBAR[0x0318]))
#define MCF5272_PLI_P3B2RR          (*(vuint32 *)(void *)(&__MBAR[0x031C]))
#define MCF5272_PLI_P0DRR           (*(vuint8  *)(void *)(&__MBAR[0x0320]))
#define MCF5272_PLI_P1DRR           (*(vuint8  *)(void *)(&__MBAR[0x0321]))
#define MCF5272_PLI_P2DRR           (*(vuint8  *)(void *)(&__MBAR[0x0322]))
#define MCF5272_PLI_P3DRR           (*(vuint8  *)(void *)(&__MBAR[0x0323]))
#define MCF5272_PLI_P0B1TR          (*(vuint32 *)(void *)(&__MBAR[0x0328]))
#define MCF5272_PLI_P1B1TR          (*(vuint32 *)(void *)(&__MBAR[0x032C]))
#define MCF5272_PLI_P2B1TR          (*(vuint32 *)(void *)(&__MBAR[0x0330]))
#define MCF5272_PLI_P3B1TR          (*(vuint32 *)(void *)(&__MBAR[0x0334]))
#define MCF5272_PLI_P0B2TR          (*(vuint32 *)(void *)(&__MBAR[0x0338]))
#define MCF5272_PLI_P1B2TR          (*(vuint32 *)(void *)(&__MBAR[0x033C]))
#define MCF5272_PLI_P2B2TR          (*(vuint32 *)(void *)(&__MBAR[0x0340]))
#define MCF5272_PLI_P3B2TR          (*(vuint32 *)(void *)(&__MBAR[0x0344]))
#define MCF5272_PLI_P0DTR           (*(vuint8  *)(void *)(&__MBAR[0x0348]))
#define MCF5272_PLI_P1DTR           (*(vuint8  *)(void *)(&__MBAR[0x0349]))
#define MCF5272_PLI_P2DTR           (*(vuint8  *)(void *)(&__MBAR[0x034A]))
#define MCF5272_PLI_P3DTR           (*(vuint8  *)(void *)(&__MBAR[0x034B]))
#define MCF5272_PLI_P0CR            (*(vuint16 *)(void *)(&__MBAR[0x0350]))
#define MCF5272_PLI_P1CR            (*(vuint16 *)(void *)(&__MBAR[0x0352]))
#define MCF5272_PLI_P2CR            (*(vuint16 *)(void *)(&__MBAR[0x0354]))
#define MCF5272_PLI_P3CR            (*(vuint16 *)(void *)(&__MBAR[0x0356]))
#define MCF5272_PLI_P0ICR           (*(vuint16 *)(void *)(&__MBAR[0x0358]))
#define MCF5272_PLI_P1ICR           (*(vuint16 *)(void *)(&__MBAR[0x035A]))
#define MCF5272_PLI_P2ICR           (*(vuint16 *)(void *)(&__MBAR[0x035C]))
#define MCF5272_PLI_P3ICR           (*(vuint16 *)(void *)(&__MBAR[0x035E]))
#define MCF5272_PLI_P0GMR           (*(vuint16 *)(void *)(&__MBAR[0x0360]))
#define MCF5272_PLI_P1GMR           (*(vuint16 *)(void *)(&__MBAR[0x0362]))
#define MCF5272_PLI_P2GMR           (*(vuint16 *)(void *)(&__MBAR[0x0364]))
#define MCF5272_PLI_P3GMR           (*(vuint16 *)(void *)(&__MBAR[0x0366]))
#define MCF5272_PLI_P0GMT           (*(vuint16 *)(void *)(&__MBAR[0x0368]))
#define MCF5272_PLI_P1GMT           (*(vuint16 *)(void *)(&__MBAR[0x036A]))
#define MCF5272_PLI_P2GMT           (*(vuint16 *)(void *)(&__MBAR[0x036C]))
#define MCF5272_PLI_P3GMT           (*(vuint16 *)(void *)(&__MBAR[0x036E]))
#define MCF5272_PLI_PGMTS           (*(vuint8  *)(void *)(&__MBAR[0x0371]))
#define MCF5272_PLI_PGMTA           (*(vuint8  *)(void *)(&__MBAR[0x0372]))
#define MCF5272_PLI_P0GCIR          (*(vuint8  *)(void *)(&__MBAR[0x0374]))
#define MCF5272_PLI_P1GCIR          (*(vuint8  *)(void *)(&__MBAR[0x0375]))
#define MCF5272_PLI_P2GCIR          (*(vuint8  *)(void *)(&__MBAR[0x0376]))
#define MCF5272_PLI_P3GCIR          (*(vuint8  *)(void *)(&__MBAR[0x0377]))
#define MCF5272_PLI_P0GCIT          (*(vuint8  *)(void *)(&__MBAR[0x0378]))
#define MCF5272_PLI_P1GCIT          (*(vuint8  *)(void *)(&__MBAR[0x0379]))