📄 mcf5272.h
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#define MCF5272_CS_CSOR4 (*(vuint32 *)(void *)(&__MBAR[0x0064]))
#define MCF5272_CS_CSBR5 (*(vuint32 *)(void *)(&__MBAR[0x0068]))
#define MCF5272_CS_CSOR5 (*(vuint32 *)(void *)(&__MBAR[0x006C]))
#define MCF5272_CS_CSBR6 (*(vuint32 *)(void *)(&__MBAR[0x0070]))
#define MCF5272_CS_CSOR6 (*(vuint32 *)(void *)(&__MBAR[0x0074]))
#define MCF5272_CS_CSBR7 (*(vuint32 *)(void *)(&__MBAR[0x0078]))
#define MCF5272_CS_CSOR7 (*(vuint32 *)(void *)(&__MBAR[0x007C]))
/* Bit level definitions and macros */
#define MCF5272_CS_BR_BASE(a) ((a)&0xFFFFF000)
#define MCF5272_CS_OR_MASK_128M (0xF8000000)
#define MCF5272_CS_OR_MASK_64M (0xFC000000)
#define MCF5272_CS_OR_MASK_32M (0xFE000000)
#define MCF5272_CS_OR_MASK_16M (0xFF000000)
#define MCF5272_CS_OR_MASK_8M (0xFF800000)
#define MCF5272_CS_OR_MASK_4M (0xFFC00000)
#define MCF5272_CS_OR_MASK_2M (0xFFE00000)
#define MCF5272_CS_OR_MASK_1M (0xFFF00000)
#define MCF5272_CS_OR_MASK_512K (0xFFF80000)
#define MCF5272_CS_OR_MASK_256K (0xFFFC0000)
#define MCF5272_CS_OR_MASK_128K (0xFFFE0000)
#define MCF5272_CS_OR_MASK_64K (0xFFFF0000)
#define MCF5272_CS_OR_MASK_32K (0xFFFF8000)
#define MCF5272_CS_OR_MASK_16K (0xFFFFC000)
#define MCF5272_CS_OR_MASK_8K (0xFFFFE000)
#define MCF5272_CS_OR_MASK_4K (0xFFFFF000)
#define MCF5272_CS_OR_WS_MASK (0x007C)
#define MCF5272_CS_OR_WS(a) (((a)&0x1F)<<2)
#define MCF5272_CS_OR_BRST (0x0100)
#define MCF5272_CS_OR_WR_ONLY (0x0003)
#define MCF5272_CS_OR_RD_ONLY (0x0001)
#define MCF5272_CS_BR_PS_8 (0x0100)
#define MCF5272_CS_BR_PS_16 (0x0200)
#define MCF5272_CS_BR_PS_32 (0x0000)
#define MCF5272_CS_BR_PS_LINE (0x0300)
#define MCF5272_CS_BR_ROM (0x0000)
#define MCF5272_CS_BR_SRAM (0x0000)
#define MCF5272_CS_BR_SRAM_8 (0x0C00)
#define MCF5272_CS_BR_SDRAM (0x0400)
#define MCF5272_CS_BR_ISA (0x0800)
#define MCF5272_CS_BR_SV (0x0080)
#define MCF5272_CS_BR_EN (0x0001)
/**********************************************************************
*
* Ports Registers Description
*
***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5272_GPIO_PACNT (*(vuint32 *)(void *)(&__MBAR[0x0080]))
#define MCF5272_GPIO_PADDR (*(vuint16 *)(void *)(&__MBAR[0x0084]))
#define MCF5272_GPIO_PADAT (*(vuint16 *)(void *)(&__MBAR[0x0086]))
#define MCF5272_GPIO_PBCNT (*(vuint32 *)(void *)(&__MBAR[0x0088]))
#define MCF5272_GPIO_PBDDR (*(vuint16 *)(void *)(&__MBAR[0x008C]))
#define MCF5272_GPIO_PBDAT (*(vuint16 *)(void *)(&__MBAR[0x008E]))
#define MCF5272_GPIO_PCDDR (*(vuint16 *)(void *)(&__MBAR[0x0094]))
#define MCF5272_GPIO_PCDAT (*(vuint16 *)(void *)(&__MBAR[0x0096]))
#define MCF5272_GPIO_PDCNT (*(vuint32 *)(void *)(&__MBAR[0x0098]))
/* Bit level definitions and macros */
#define MCF5272_GPIO_DDR15_INPUT (~0x80)
#define MCF5272_GPIO_DDR15_OUTPUT ( 0x80)
#define MCF5272_GPIO_DDR14_INPUT (~0x40)
#define MCF5272_GPIO_DDR14_OUTPUT ( 0x40)
#define MCF5272_GPIO_DDR13_INPUT (~0x20)
#define MCF5272_GPIO_DDR13_OUTPUT ( 0x20)
#define MCF5272_GPIO_DDR12_INPUT (~0x10)
#define MCF5272_GPIO_DDR12_OUTPUT ( 0x10)
#define MCF5272_GPIO_DDR11_INPUT (~0x08)
#define MCF5272_GPIO_DDR11_OUTPUT ( 0x08)
#define MCF5272_GPIO_DDR10_INPUT (~0x04)
#define MCF5272_GPIO_DDR10_OUTPUT ( 0x04)
#define MCF5272_GPIO_DDR9_INPUT (~0x02)
#define MCF5272_GPIO_DDR9_OUTPUT ( 0x02)
#define MCF5272_GPIO_DDR8_INPUT (~0x01)
#define MCF5272_GPIO_DDR8_OUTPUT ( 0x01)
#define MCF5272_GPIO_DDR7_INPUT (~0x80)
#define MCF5272_GPIO_DDR7_OUTPUT ( 0x80)
#define MCF5272_GPIO_DDR6_INPUT (~0x40)
#define MCF5272_GPIO_DDR6_OUTPUT ( 0x40)
#define MCF5272_GPIO_DDR5_INPUT (~0x20)
#define MCF5272_GPIO_DDR5_OUTPUT ( 0x20)
#define MCF5272_GPIO_DDR4_INPUT (~0x10)
#define MCF5272_GPIO_DDR4_OUTPUT ( 0x10)
#define MCF5272_GPIO_DDR3_INPUT (~0x08)
#define MCF5272_GPIO_DDR3_OUTPUT ( 0x08)
#define MCF5272_GPIO_DDR2_INPUT (~0x04)
#define MCF5272_GPIO_DDR2_OUTPUT ( 0x04)
#define MCF5272_GPIO_DDR1_INPUT (~0x02)
#define MCF5272_GPIO_DDR1_OUTPUT ( 0x02)
#define MCF5272_GPIO_DDR0_INPUT (~0x01)
#define MCF5272_GPIO_DDR0_OUTPUT ( 0x01)
#define MCF5272_GPIO_DAT15 ( 0x80)
#define MCF5272_GPIO_DAT14 ( 0x40)
#define MCF5272_GPIO_DAT13 ( 0x20)
#define MCF5272_GPIO_DAT12 ( 0x10)
#define MCF5272_GPIO_DAT11 ( 0x08)
#define MCF5272_GPIO_DAT10 ( 0x04)
#define MCF5272_GPIO_DAT9 ( 0x02)
#define MCF5272_GPIO_DAT8 ( 0x01)
#define MCF5272_GPIO_DAT7 ( 0x80)
#define MCF5272_GPIO_DAT6 ( 0x40)
#define MCF5272_GPIO_DAT5 ( 0x20)
#define MCF5272_GPIO_DAT4 ( 0x10)
#define MCF5272_GPIO_DAT3 ( 0x08)
#define MCF5272_GPIO_DAT2 ( 0x04)
#define MCF5272_GPIO_DAT1 ( 0x02)
#define MCF5272_GPIO_DAT0 ( 0x01)
/**********************************************************************
*
* QSPI Module Registers Description
*
***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5272_QSPI_QMR (*(vuint16 *)(void *)(&__MBAR[0x00A0]))
#define MCF5272_QSPI_QDLYR (*(vuint16 *)(void *)(&__MBAR[0x00A4]))
#define MCF5272_QSPI_QWR (*(vuint16 *)(void *)(&__MBAR[0x00A8]))
#define MCF5272_QSPI_QIR (*(vuint16 *)(void *)(&__MBAR[0x00AC]))
#define MCF5272_QSPI_QAR (*(vuint16 *)(void *)(&__MBAR[0x00B0]))
#define MCF5272_QSPI_QDR (*(vuint16 *)(void *)(&__MBAR[0x00B4]))
/* Bit level definitions and macros */
#define MCF5272_QSPI_QMR_MSTR (0x8000)
#define MCF5272_QSPI_QMR_DOHIE (0x4000)
#define MCF5272_QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
#define MCF5272_QSPI_QMR_CPOL (0x0200)
#define MCF5272_QSPI_QMR_CPHA (0x0100)
#define MCF5272_QSPI_QMR_BAUD(x) (((x)&0x00FF))
#define MCF5272_QSPI_QDLYR_SPE (0x80)
#define MCF5272_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
#define MCF5272_QSPI_QDLYR_DTL(x) (((x)&0x00FF))
#define MCF5272_QSPI_QWR_HALT (0x8000)
#define MCF5272_QSPI_QWR_WREN (0x4000)
#define MCF5272_QSPI_QWR_WRTO (0x2000)
#define MCF5272_QSPI_QWR_CSIV (0x1000)
#define MCF5272_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
#define MCF5272_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
#define MCF5272_QSPI_QWR_NEWQP(x) (((x)&0x000F))
#define MCF5272_QSPI_QIR_WCEFB (0x8000)
#define MCF5272_QSPI_QIR_ABRTB (0x4000)
#define MCF5272_QSPI_QIR_ABRTL (0x1000)
#define MCF5272_QSPI_QIR_WCEFE (0x0800)
#define MCF5272_QSPI_QIR_ABRTE (0x0400)
#define MCF5272_QSPI_QIR_SPIFE (0x0100)
#define MCF5272_QSPI_QIR_WCEF (0x0008)
#define MCF5272_QSPI_QIR_ABRT (0x0004)
#define MCF5272_QSPI_QIR_SPIF (0x0001)
#define MCF5272_QSPI_QAR_ADDR(x) (((x)&0x003F))
#define MCF5272_QSPI_QDR_DATA(x) (((x)&0xFFFF))
#define MCF5272_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8)
#define MCF5272_QSPI_QCR_CONT (0x8000)
#define MCF5272_QSPI_QCR_BITSE (0x4000)
#define MCF5272_QSPI_QCR_DT (0x2000)
#define MCF5272_QSPI_QCR_DSCK (0x1000)
#define MCF5272_QSPI_QCR_CS (((x)&0x000F)<<8)
/**********************************************************************
*
* PWM Module Registers Description
*
***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5272_PWM_PWCR0 (*(vuint8 *)(void *)(&__MBAR[0x00C0]))
#define MCF5272_PWM_PWCR1 (*(vuint8 *)(void *)(&__MBAR[0x00C4]))
#define MCF5272_PWM_PWCR2 (*(vuint8 *)(void *)(&__MBAR[0x00C8]))
#define MCF5272_PWM_PWWD0 (*(vuint8 *)(void *)(&__MBAR[0x00D0]))
#define MCF5272_PWM_PWWD1 (*(vuint8 *)(void *)(&__MBAR[0x00D4]))
#define MCF5272_PWM_PWWD2 (*(vuint8 *)(void *)(&__MBAR[0x00D8]))
/**********************************************************************
*
* DMA Module Registers Description
*
***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5272_DMA_DCMR (*(vuint32 *)(void *)(&__MBAR[0x00E0]))
#define MCF5272_DMA_DCIR (*(vuint16 *)(void *)(&__MBAR[0x00E6]))
#define MCF5272_DMA_DBCR (*(vuint32 *)(void *)(&__MBAR[0x00E8]))
#define MCF5272_DMA_DSAR (*(vuint32 *)(void *)(&__MBAR[0x00EC]))
#define MCF5272_DMA_DDAR (*(vuint32 *)(void *)(&__MBAR[0x00F0]))
/* Bit level definitions and macros */
#define MCF5272_DMA_DCMR_RESET (0x80000000)
#define MCF5272_DMA_DCMR_EN (0x40000000)
#define MCF5272_DMA_DCMR_RQM (0x000C0000)
#define MCF5272_DMA_DCMR_DSTM_INC (0x00002000)
#define MCF5272_DMA_DCMR_DSTT_UD (0x00000400)
#define MCF5272_DMA_DCMR_DSTT_UC (0x00000800)
#define MCF5272_DMA_DCMR_DSTT_SD (0x00001400)
#define MCF5272_DMA_DCMR_DSTT_SC (0x00001800)
#define MCF5272_DMA_DCMR_DSTS_LW (0x00000000)
#define MCF5272_DMA_DCMR_DSTS_B (0x00000100)
#define MCF5272_DMA_DCMR_DSTS_W (0x00000200)
#define MCF5272_DMA_DCMR_DSTS_LINE (0x00000300)
#define MCF5272_DMA_DCMR_SRCM_INC (0x00000020)
#define MCF5272_DMA_DCMR_SRCT_UD (0x00000004)
#define MCF5272_DMA_DCMR_SRCT_UC (0x00000008)
#define MCF5272_DMA_DCMR_SRCT_SD (0x00000014)
#define MCF5272_DMA_DCMR_SRCT_SC (0x00000018)
#define MCF5272_DMA_DCMR_SRCS_LW (0x00000000)
#define MCF5272_DMA_DCMR_SRCS_B (0x00000001)
#define MCF5272_DMA_DCMR_SRCS_W (0x00000002)
#define MCF5272_DMA_DCMR_SRCS_LINE (0x00000003)
#define MCF5272_DMA_DCIR_INVEN (0x1000)
#define MCF5272_DMA_DCIR_ASCEN (0x0800)
#define MCF5272_DMA_DCIR_TEEN (0x0200)
#define MCF5272_DMA_DCIR_TCEN (0x0100)
#define MCF5272_DMA_DCIR_INV (0x0010)
#define MCF5272_DMA_DCIR_ASC (0x0008)
#define MCF5272_DMA_DCIR_TE (0x0002)
#define MCF5272_DMA_DCIR_TC (0x0001)
/**********************************************************************
*
* UART Module Registers Description
*
***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5272_UART0_UMR (*(vuint8 *)(void *)(&__MBAR[0x0100])) /* RW */
#define MCF5272_UART0_USR (*(vuint8 *)(void *)(&__MBAR[0x0104])) /* USR RO */
#define MCF5272_UART0_UCSR (*(vuint8 *)(void *)(&__MBAR[0x0104])) /* UCSR WO */
#define MCF5272_UART0_UCR (*(vuint8 *)(void *)(&__MBAR[0x0108])) /* WO */
#define MCF5272_UART0_URB (*(vuint8 *)(void *)(&__MBAR[0x010C])) /* URB RO */
#define MCF5272_UART0_UTB (*(vuint8 *)(void *)(&__MBAR[0x010C])) /* UTB WO */
#define MCF5272_UART0_UIPCR (*(vuint8 *)(void *)(&__MBAR[0x0110])) /* UIPCR RO */
#define MCF5272_UART0_UACR (*(vuint8 *)(void *)(&__MBAR[0x0110])) /* UACR WO */
#define MCF5272_UART0_UISR (*(vuint8 *)(void *)(&__MBAR[0x0114])) /* UISR RO */
#define MCF5272_UART0_UIMR (*(vuint8 *)(void *)(&__MBAR[0x0114])) /* UIMR WO */
#define MCF5272_UART0_UBG1 (*(vuint8 *)(void *)(&__MBAR[0x0118])) /* WO */
#define MCF5272_UART0_UBG2 (*(vuint8 *)(void *)(&__MBAR[0x011C])) /* WO */
#define MCF5272_UART0_UABR1 (*(vuint8 *)(void *)(&__MBAR[0x0120])) /* RO */
#define MCF5272_UART0_UABR2 (*(vuint8 *)(void *)(&__MBAR[0x0124])) /* RO */
#define MCF5272_UART0_UTFCSR (*(vuint8 *)(void *)(&__MBAR[0x0128])) /* RW */
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