📄 mcf5272.h
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/*
* File: src/include/cpu/coldfire/mcf5272.h
* Purpose: MCF5272 definitions
*
* Notes: This file automatically included.
* __MBAR must be defined in dbug/proj/<board>/src/<board>.h
*/
#ifndef _CPU_MCF5272_H
#define _CPU_MCF5272_H
/**********************************************************************
*
* System Configuration Registers
*
***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5272_SIM_MBAR (*(vuint32 *)(void *)(&__MBAR[0x0000]))
#define MCF5272_SIM_SCR (*(vuint16 *)(void *)(&__MBAR[0x0004]))
#define MCF5272_SIM_SPR (*(vuint16 *)(void *)(&__MBAR[0x0006]))
#define MCF5272_SIM_PMR (*(vuint32 *)(void *)(&__MBAR[0x0008]))
#define MCF5272_SIM_ALPR (*(vuint16 *)(void *)(&__MBAR[0x000E]))
#define MCF5272_SIM_DIR (*(vuint32 *)(void *)(&__MBAR[0x0010]))
/* Bit level definitions and macros */
#define MCF5272_SIM_SCR_HRST 0x1000
#define MCF5272_SIM_SCR_DRAMRST 0x3000
#define MCF5272_SIM_SCR_SWTR 0x2000
#define MCF5272_SIM_SCR_AR 0x0080
#define MCF5272_SIM_SCR_SOFT_RES 0x0040
#define MCF5272_SIM_SCR_HWWD_128 0x0000
#define MCF5272_SIM_SCR_HWWD_256 0x0001
#define MCF5272_SIM_SCR_HWWD_512 0x0002
#define MCF5272_SIM_SCR_HWWD_1024 0x0003
#define MCF5272_SIM_SCR_HWWD_2048 0x0004
#define MCF5272_SIM_SCR_HWWD_4096 0x0005
#define MCF5272_SIM_SCR_HWWD_8192 0x0006
#define MCF5272_SIM_SCR_HWWD_16384 0x0007
#define MCF5272_SIM_SPR_ADC 0x8000
#define MCF5272_SIM_SPR_ADCEN 0x0080
#define MCF5272_SIM_SPR_WPV 0x4000
#define MCF5272_SIM_SPR_WPVEN 0x0040
#define MCF5272_SIM_SPR_SMV 0x2000
#define MCF5272_SIM_SPR_SMVEN 0x0020
#define MCF5272_SIM_SPR_SBE 0x1000
#define MCF5272_SIM_SPR_SBEEN 0x0010
#define MCF5272_SIM_SPR_HWT 0x0800
#define MCF5272_SIM_SPR_HWTEN 0x0008
#define MCF5272_SIM_SPR_RPV 0x0400
#define MCF5272_SIM_SPR_RPVEN 0x0004
#define MCF5272_SIM_SPR_EXT 0x0200
#define MCF5272_SIM_SPR_EXTEN 0x0002
#define MCF5272_SIM_SPR_SUV 0x0100
#define MCF5272_SIM_SPR_SUVEN 0x0001
#define MCF5272_SIM_PMR_BDMPDN 0x80000000
#define MCF5272_SIM_PMR_ENETPDN 0x04000000
#define MCF5272_SIM_PMR_PLIPPDN 0x02000000
#define MCF5272_SIM_PMR_DRAMPDN 0x01000000
#define MCF5272_SIM_PMR_DMAPDN 0x00800000
#define MCF5272_SIM_PMR_PWMPDN 0x00400000
#define MCF5272_SIM_PMR_QSPIPDN 0x00200000
#define MCF5272_SIM_PMR_TIMERPDN 0x00100000
#define MCF5272_SIM_PMR_GPIOPDN 0x00080000
#define MCF5272_SIM_PMR_USBPDN 0x00040000
#define MCF5272_SIM_PMR_UART1PDN 0x00020000
#define MCF5272_SIM_PMR_UART0PDN 0x00010000
#define MCF5272_SIM_PMR_USBWK 0x00000400
#define MCF5272_SIM_PMR_UART1WK 0x00000200
#define MCF5272_SIM_PMR_UART0WK 0x00000100
#define MCF5272_SIM_PMR_MOS 0x00000020
#define MCF5272_SIM_PMR_SLPEN 0x00000010
/*********************************************************************
*
* Interrupt Controller (INTC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF5272_INTC_ICR1 (*(vuint32*)(void*)(&__MBAR[0x000020]))
#define MCF5272_INTC_ICR2 (*(vuint32*)(void*)(&__MBAR[0x000024]))
#define MCF5272_INTC_ICR3 (*(vuint32*)(void*)(&__MBAR[0x000028]))
#define MCF5272_INTC_ICR4 (*(vuint32*)(void*)(&__MBAR[0x00002C]))
#define MCF5272_INTC_ISR (*(vuint32*)(void*)(&__MBAR[0x000030]))
#define MCF5272_INTC_PITR (*(vuint32*)(void*)(&__MBAR[0x000034]))
#define MCF5272_INTC_PIWR (*(vuint32*)(void*)(&__MBAR[0x000038]))
#define MCF5272_INTC_PIVR (*(vuint8 *)(void*)(&__MBAR[0x00003F]))
/* Bit definitions and macros for all ICRs */
#define MCF5272_INTC_ICR_IPL_ALL (0x77777777)
#define MCF5272_INTC_ICR_IP_ALL (0x88888888)
/* Bit definitions and macros for MCF5272_INTC_ICR1 */
#define MCF5272_INTC_ICR1_TMR3IPL(x) (((x)&0x00000007)<<0)
#define MCF5272_INTC_ICR1_TMR3PI (0x00000008)
#define MCF5272_INTC_ICR1_TMR2IPL(x) (((x)&0x00000007)<<4)
#define MCF5272_INTC_ICR1_TMR2PI (0x00000080)
#define MCF5272_INTC_ICR1_TMR1IPL(x) (((x)&0x00000007)<<8)
#define MCF5272_INTC_ICR1_TMR1PI (0x00000800)
#define MCF5272_INTC_ICR1_TMR0IPL(x) (((x)&0x00000007)<<12)
#define MCF5272_INTC_ICR1_TMR0PI (0x00008000)
#define MCF5272_INTC_ICR1_INT4IPL(x) (((x)&0x00000007)<<16)
#define MCF5272_INTC_ICR1_INT4PI (0x00080000)
#define MCF5272_INTC_ICR1_INT3IPL(x) (((x)&0x00000007)<<20)
#define MCF5272_INTC_ICR1_INT3PI (0x00800000)
#define MCF5272_INTC_ICR1_INT2IPL(x) (((x)&0x00000007)<<24)
#define MCF5272_INTC_ICR1_INT2PI (0x08000000)
#define MCF5272_INTC_ICR1_INT1IPL(x) (((x)&0x00000007)<<28)
#define MCF5272_INTC_ICR1_INT1PI (0x80000000)
#define MCF5272_INTC_ICR1_TMR_IPL(a,x) (((a)&0x07) << ((3-x)*4))
#define MCF5272_INTC_ICR1_TMR_IP(x) (0x8 << ((3-x)*4))
/* Bit definitions and macros for MCF5272_INTC_ICR2 */
#define MCF5272_INTC_ICR2_USB3IPL(x) (((x)&0x00000007)<<0)
#define MCF5272_INTC_ICR2_USB3PI (0x00000008)
#define MCF5272_INTC_ICR2_USB2IPL(x) (((x)&0x00000007)<<4)
#define MCF5272_INTC_ICR2_USB2PI (0x00000080)
#define MCF5272_INTC_ICR2_USB1IPL(x) (((x)&0x00000007)<<8)
#define MCF5272_INTC_ICR2_USB1PI (0x00000800)
#define MCF5272_INTC_ICR2_USB0IPL(x) (((x)&0x00000007)<<12)
#define MCF5272_INTC_ICR2_USB0PI (0x00008000)
#define MCF5272_INTC_ICR2_PLIA4IPL(x) (((x)&0x00000007)<<16)
#define MCF5272_INTC_ICR2_PLIA4PI (0x00080000)
#define MCF5272_INTC_ICR2_PLIPIPL(x) (((x)&0x00000007)<<20)
#define MCF5272_INTC_ICR2_PLIPPI (0x00800000)
#define MCF5272_INTC_ICR2_UART1IPL(x) (((x)&0x00000007)<<24)
#define MCF5272_INTC_ICR2_UART1PI (0x08000000)
#define MCF5272_INTC_ICR2_UART0IPL(x) (((x)&0x00000007)<<28)
#define MCF5272_INTC_ICR2_UART0PI (0x80000000)
/* Bit definitions and macros for MCF5272_INTC_ICR3 */
#define MCF5272_INTC_ICR3_ENTCIPL(x) (((x)&0x00000007)<<0)
#define MCF5272_INTC_ICR3_ENTCPI (0x00000008)
#define MCF5272_INTC_ICR3_ETXIPL(x) (((x)&0x00000007)<<4)
#define MCF5272_INTC_ICR3_ETXPI (0x00000080)
#define MCF5272_INTC_ICR3_ERXIPL(x) (((x)&0x00000007)<<8)
#define MCF5272_INTC_ICR3_ERXPI (0x00000800)
#define MCF5272_INTC_ICR3_DMAIPL(x) (((x)&0x00000007)<<12)
#define MCF5272_INTC_ICR3_DMAPI (0x00008000)
#define MCF5272_INTC_ICR3_USB7IPL(x) (((x)&0x00000007)<<16)
#define MCF5272_INTC_ICR3_USB7PI (0x00080000)
#define MCF5272_INTC_ICR3_USB6IPL(x) (((x)&0x00000007)<<20)
#define MCF5272_INTC_ICR3_USB6PI (0x00800000)
#define MCF5272_INTC_ICR3_USB5IPL(x) (((x)&0x00000007)<<24)
#define MCF5272_INTC_ICR3_USB5PI (0x08000000)
#define MCF5272_INTC_ICR3_USB4IPL(x) (((x)&0x00000007)<<28)
#define MCF5272_INTC_ICR3_USB4PI (0x80000000)
/* Bit definitions and macros for MCF5272_INTC_ICR4 */
#define MCF5272_INTC_ICR4_SWTOIPL(x) (((x)&0x00000007)<<16)
#define MCF5272_INTC_ICR4_SWTOPI (0x00080000)
#define MCF5272_INTC_ICR4_INT6IPL(x) (((x)&0x00000007)<<20)
#define MCF5272_INTC_ICR4_INT6PI (0x00800000)
#define MCF5272_INTC_ICR4_INT5IPL(x) (((x)&0x00000007)<<24)
#define MCF5272_INTC_ICR4_INT5PI (0x08000000)
#define MCF5272_INTC_ICR4_QSPIIPL(x) (((x)&0x00000007)<<28)
#define MCF5272_INTC_ICR4_QSPIPI (0x80000000)
/* Bit definitions and macros for MCF5272_INTC_ISR */
#define MCF5272_INTC_ISR_SWTO (0x00000010)
#define MCF5272_INTC_ISR_INT6 (0x00000020)
#define MCF5272_INTC_ISR_INT5 (0x00000040)
#define MCF5272_INTC_ISR_QSPI (0x00000080)
#define MCF5272_INTC_ISR_ENTC (0x00000100)
#define MCF5272_INTC_ISR_ETX (0x00000200)
#define MCF5272_INTC_ISR_ERX (0x00000400)
#define MCF5272_INTC_ISR_DMA (0x00000800)
#define MCF5272_INTC_ISR_USB7 (0x00001000)
#define MCF5272_INTC_ISR_USB6 (0x00002000)
#define MCF5272_INTC_ISR_USB5 (0x00004000)
#define MCF5272_INTC_ISR_USB4 (0x00008000)
#define MCF5272_INTC_ISR_USB3 (0x00010000)
#define MCF5272_INTC_ISR_USB2 (0x00020000)
#define MCF5272_INTC_ISR_USB1 (0x00040000)
#define MCF5272_INTC_ISR_USB0 (0x00080000)
#define MCF5272_INTC_ISR_PLI_A (0x00100000)
#define MCF5272_INTC_ISR_PLI_P (0x00200000)
#define MCF5272_INTC_ISR_UART1 (0x00400000)
#define MCF5272_INTC_ISR_UART0 (0x00800000)
#define MCF5272_INTC_ISR_TMR3 (0x01000000)
#define MCF5272_INTC_ISR_TMR2 (0x02000000)
#define MCF5272_INTC_ISR_TMR1 (0x04000000)
#define MCF5272_INTC_ISR_TMR0 (0x08000000)
#define MCF5272_INTC_ISR_INT4 (0x10000000)
#define MCF5272_INTC_ISR_INT3 (0x20000000)
#define MCF5272_INTC_ISR_INT2 (0x40000000)
#define MCF5272_INTC_ISR_INT1 (0x80000000)
/* Bit definitions and macros for MCF5272_INTC_PITR */
#define MCF5272_INTC_PITR_INT6 (0x00000020)
#define MCF5272_INTC_PITR_INT5 (0x00000040)
#define MCF5272_INTC_PITR_INT4 (0x10000000)
#define MCF5272_INTC_PITR_INT3 (0x20000000)
#define MCF5272_INTC_PITR_INT2 (0x40000000)
#define MCF5272_INTC_PITR_INT1 (0x80000000)
/* Bit definitions and macros for MCF5272_INTC_PIWR */
#define MCF5272_INTC_PIWR_SWTO (0x00000010)
#define MCF5272_INTC_PIWR_INT6 (0x00000020)
#define MCF5272_INTC_PIWR_INT5 (0x00000040)
#define MCF5272_INTC_PIWR_QSPI (0x00000080)
#define MCF5272_INTC_PIWR_ENTC (0x00000100)
#define MCF5272_INTC_PIWR_ETX (0x00000200)
#define MCF5272_INTC_PIWR_ERX (0x00000400)
#define MCF5272_INTC_PIWR_DMA (0x00000800)
#define MCF5272_INTC_PIWR_USB7 (0x00001000)
#define MCF5272_INTC_PIWR_USB6 (0x00002000)
#define MCF5272_INTC_PIWR_USB5 (0x00004000)
#define MCF5272_INTC_PIWR_USB4 (0x00008000)
#define MCF5272_INTC_PIWR_USB3 (0x00010000)
#define MCF5272_INTC_PIWR_USB2 (0x00020000)
#define MCF5272_INTC_PIWR_USB1 (0x00040000)
#define MCF5272_INTC_PIWR_USB0 (0x00080000)
#define MCF5272_INTC_PIWR_PLI_A (0x00100000)
#define MCF5272_INTC_PIWR_PLI_P (0x00200000)
#define MCF5272_INTC_PIWR_UART2 (0x00400000)
#define MCF5272_INTC_PIWR_UART1 (0x00800000)
#define MCF5272_INTC_PIWR_TMR3 (0x01000000)
#define MCF5272_INTC_PIWR_TMR2 (0x02000000)
#define MCF5272_INTC_PIWR_TMR1 (0x04000000)
#define MCF5272_INTC_PIWR_TMR0 (0x08000000)
#define MCF5272_INTC_PIWR_INT4 (0x10000000)
#define MCF5272_INTC_PIWR_INT3 (0x20000000)
#define MCF5272_INTC_PIWR_INT2 (0x40000000)
#define MCF5272_INTC_PIWR_INT1 (0x80000000)
/* Bit definitions and macros for MCF5272_INTC_PIVR */
#define MCF5272_INTC_PIVR_IV(x) (((x)&0x07)<<5)
#define MCF5272_INTC_PIVR_NORMAL MCF5272_INTC_PIVR_IV(2)
/**********************************************************************
*
* Chip Select Registers
*
***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5272_CS_CSBR0 (*(vuint32 *)(void *)(&__MBAR[0x0040]))
#define MCF5272_CS_CSOR0 (*(vuint32 *)(void *)(&__MBAR[0x0044]))
#define MCF5272_CS_CSBR1 (*(vuint32 *)(void *)(&__MBAR[0x0048]))
#define MCF5272_CS_CSOR1 (*(vuint32 *)(void *)(&__MBAR[0x004C]))
#define MCF5272_CS_CSBR2 (*(vuint32 *)(void *)(&__MBAR[0x0050]))
#define MCF5272_CS_CSOR2 (*(vuint32 *)(void *)(&__MBAR[0x0054]))
#define MCF5272_CS_CSBR3 (*(vuint32 *)(void *)(&__MBAR[0x0058]))
#define MCF5272_CS_CSOR3 (*(vuint32 *)(void *)(&__MBAR[0x005C]))
#define MCF5272_CS_CSBR4 (*(vuint32 *)(void *)(&__MBAR[0x0060]))
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