mcf5307.h

motorola 针对coldfire 5275 评估板的Dbug bootloader源程序

#define MCF5307_UART_UMR2_CM_REMOTE_LOOP    (0xC0)
#define MCF5307_UART_UMR2_TXRTS         (0x20)
#define MCF5307_UART_UMR2_TXCTS         (0x10)
#define MCF5307_UART_UMR2_STOP_BITS_1   (0x07)
#define MCF5307_UART_UMR2_STOP_BITS_15  (0x08)
#define MCF5307_UART_UMR2_STOP_BITS_2   (0x0F)
#define MCF5307_UART_UMR2_STOP_BITS(a)   ((a)&0x0f)

#define MCF5307_UART_USR_RB             (0x80)
#define MCF5307_UART_USR_FE             (0x40)
#define MCF5307_UART_USR_PE             (0x20)
#define MCF5307_UART_USR_OE             (0x10)
#define MCF5307_UART_USR_TXEMP          (0x08)
#define MCF5307_UART_USR_TXRDY          (0x04)
#define MCF5307_UART_USR_FFULL          (0x02)
#define MCF5307_UART_USR_RXRDY          (0x01)

#define MCF5307_UART_UCSR_RCS(a)        (((a)&0x0f)<<4)
#define MCF5307_UART_UCSR_TCS(a)        ((a)&0x0f)

#define MCF5307_UART_UCR_NONE           (0x00)
#define MCF5307_UART_UCR_STOP_BREAK     (0x70)
#define MCF5307_UART_UCR_START_BREAK    (0x60)
#define MCF5307_UART_UCR_RESET_BKCHGINT (0x50)
#define MCF5307_UART_UCR_RESET_ERROR    (0x40)
#define MCF5307_UART_UCR_RESET_TX       (0x30)
#define MCF5307_UART_UCR_RESET_RX       (0x20)
#define MCF5307_UART_UCR_RESET_MR       (0x10)
#define MCF5307_UART_UCR_TX_DISABLED    (0x08)
#define MCF5307_UART_UCR_TX_ENABLED     (0x04)
#define MCF5307_UART_UCR_RX_DISABLED    (0x02)
#define MCF5307_UART_UCR_RX_ENABLED     (0x01)

#define MCF5307_UART_UCCR_COS           (0x10)
#define MCF5307_UART_UCCR_CTS           (0x01)

#define MCF5307_UART_UACR_BRG           (0x80)
#define MCF5307_UART_UACR_CTMS_TIMER    (0x60)
#define MCF5307_UART_UACR_IEC           (0x01)

#define MCF5307_UART_UISR_COS           (0x80)
#define MCF5307_UART_UISR_DB            (0x04)
#define MCF5307_UART_UISR_RXRDY         (0x02)
#define MCF5307_UART_UISR_TXRDY         (0x01)

#define MCF5307_UART_UIMR_COS           (0x80)
#define MCF5307_UART_UIMR_DB            (0x04)
#define MCF5307_UART_UIMR_FFULL         (0x02)
#define MCF5307_UART_UIMR_TXRDY         (0x01)

/***********************************************************************/
/*  I2C (I-squared C) Registers                                        */
/***********************************************************************/

/* Read/Write access macros for general use */
#define MCF5307_I2C_IADR        (*(vuint8  *)(void *)(&__MBAR[0x0280]))
#define MCF5307_I2C_IFDR        (*(vuint8  *)(void *)(&__MBAR[0x0284]))
#define MCF5307_I2C_I2CR        (*(vuint8  *)(void *)(&__MBAR[0x0288]))
#define MCF5307_I2C_I2SR        (*(vuint8  *)(void *)(&__MBAR[0x028C]))
#define MCF5307_I2C_I2DR        (*(vuint8  *)(void *)(&__MBAR[0x0290]))

/* Bit level definitions and macros */
#define MCF5307_I2C_IADR_ADDR(a)    (((a)&0xFE)<<0x01)

#define MCF5307_I2C_IFDR_MBC(a) ((a)&0x3F)

#define MCF5307_I2C_I2CR_MEN        (0x80)
#define MCF5307_I2C_I2CR_MIEN       (0x40)
#define MCF5307_I2C_I2CR_MSTA       (0x20)
#define MCF5307_I2C_I2CR_MTX        (0x10)
#define MCF5307_I2C_I2CR_TXAK       (0x08)
#define MCF5307_I2C_I2CR_RSTA       (0x04)

#define MCF5307_I2C_I2SR_MCF        (0x80)
#define MCF5307_I2C_I2SR_MAAS       (0x40)
#define MCF5307_I2C_I2SR_MBB        (0x20)
#define MCF5307_I2C_I2SR_MAL        (0x10)
#define MCF5307_I2C_I2SR_SRW        (0x04)
#define MCF5307_I2C_I2SR_MIF        (0x02)
#define MCF5307_I2C_I2SR_RXAK       (0x01)

/***********************************************************************/
/*  Timer Registers                                                    */
/***********************************************************************/

/* Read/Write access macros for general use */
#define MCF5307_TIMER0_TMR      (*(vuint16 *)(void *)(&__MBAR[0x0140]))
#define MCF5307_TIMER0_TRR      (*(vuint16 *)(void *)(&__MBAR[0x0144]))
#define MCF5307_TIMER0_TCR      (*(vuint16 *)(void *)(&__MBAR[0x0148]))
#define MCF5307_TIMER0_TCN      (*(vuint16 *)(void *)(&__MBAR[0x014C]))
#define MCF5307_TIMER0_TER      (*(vuint8  *)(void *)(&__MBAR[0x0151]))

#define MCF5307_TIMER1_TMR      (*(vuint16 *)(void *)(&__MBAR[0x0180]))
#define MCF5307_TIMER1_TRR      (*(vuint16 *)(void *)(&__MBAR[0x0184]))
#define MCF5307_TIMER1_TCR      (*(vuint16 *)(void *)(&__MBAR[0x0188]))
#define MCF5307_TIMER1_TCN      (*(vuint16 *)(void *)(&__MBAR[0x018C]))
#define MCF5307_TIMER1_TER      (*(vuint8  *)(void *)(&__MBAR[0x0191]))

#define MCF5307_TIMER_TMR(x)    (*(vuint16 *)(void *)(&__MBAR[0x0140+(x*40)]))
#define MCF5307_TIMER_TRR(x)    (*(vuint16 *)(void *)(&__MBAR[0x0144+(x*40)]))
#define MCF5307_TIMER_TCR(x)    (*(vuint16 *)(void *)(&__MBAR[0x0148+(x*40)]))
#define MCF5307_TIMER_TCN(x)    (*(vuint16 *)(void *)(&__MBAR[0x014C+(x*40)]))
#define MCF5307_TIMER_TER(x)    (*(vuint8  *)(void *)(&__MBAR[0x0151+(x*40)]))

/* Bit level definitions and macros */
#define MCF5307_TIMER_TMR_PS(a)     (((a)&0x00FF)<<8)
#define MCF5307_TIMER_TMR_CE_ANY    (0x00C0)
#define MCF5307_TIMER_TMR_CE_FALL   (0x0080)
#define MCF5307_TIMER_TMR_CE_RISE   (0x0040)
#define MCF5307_TIMER_TMR_CE_NONE   (0x0000)
#define MCF5307_TIMER_TMR_OM        (0x0020)
#define MCF5307_TIMER_TMR_ORI       (0x0010)
#define MCF5307_TIMER_TMR_FRR       (0x0008)
#define MCF5307_TIMER_TMR_CLK_TIN   (0x0006)
#define MCF5307_TIMER_TMR_CLK_DIV16 (0x0004)
#define MCF5307_TIMER_TMR_CLK_MSCLK (0x0002)
#define MCF5307_TIMER_TMR_CLK_STOP  (0x0000)
#define MCF5307_TIMER_TMR_RST       (0x0001)

#define MCF5307_TIMER_TER_REF       (0x02)
#define MCF5307_TIMER_TER_CAP       (0x01)

/***********************************************************************/
/*  DMA Registers                                                      */
/***********************************************************************/

/* Read/Write access macros for general use */
#define MCF5307_DMA0_SAR        (*(vuint32 *)(void *)(&__MBAR[0x0300]))
#define MCF5307_DMA0_DAR        (*(vuint32 *)(void *)(&__MBAR[0x0304]))
#define MCF5307_DMA0_DCR        (*(vuint16 *)(void *)(&__MBAR[0x0308]))
#if (defined(CPU_MCF5307j20))
#define MCF5307_DMA0_BCR        (*(vuint32 *)(void *)(&__MBAR[0x030C]))
#else
#define MCF5307_DMA0_BCR        (*(vuint16 *)(void *)(&__MBAR[0x030C]))
#endif
#define MCF5307_DMA0_DSR        (*(vuint8  *)(void *)(&__MBAR[0x0310]))
#define MCF5307_DMA0_DIVR       (*(vuint8  *)(void *)(&__MBAR[0x0314]))

#define MCF5307_DMA1_SAR        (*(vuint32 *)(void *)(&__MBAR[0x0340]))
#define MCF5307_DMA1_DAR        (*(vuint32 *)(void *)(&__MBAR[0x0344]))
#define MCF5307_DMA1_DCR        (*(vuint16 *)(void *)(&__MBAR[0x0348]))
#if (defined(CPU_MCF5307j20))
#define MCF5307_DMA1_BCR        (*(vuint32 *)(void *)(&__MBAR[0x030C]))
#else
#define MCF5307_DMA1_BCR        (*(vuint16 *)(void *)(&__MBAR[0x030C]))
#endif
#define MCF5307_DMA1_DSR        (*(vuint8  *)(void *)(&__MBAR[0x0350]))
#define MCF5307_DMA1_DIVR       (*(vuint8  *)(void *)(&__MBAR[0x0354]))

#define MCF5307_DMA2_SAR        (*(vuint32 *)(void *)(&__MBAR[0x0380]))
#define MCF5307_DMA2_DAR        (*(vuint32 *)(void *)(&__MBAR[0x0384]))
#define MCF5307_DMA2_DCR        (*(vuint16 *)(void *)(&__MBAR[0x0388]))
#if (defined(CPU_MCF5307j20))
#define MCF5307_DMA2_BCR        (*(vuint32 *)(void *)(&__MBAR[0x030C]))
#else
#define MCF5307_DMA2_BCR        (*(vuint16 *)(void *)(&__MBAR[0x030C]))
#endif
#define MCF5307_DMA2_DSR        (*(vuint8  *)(void *)(&__MBAR[0x0390]))
#define MCF5307_DMA2_DIVR       (*(vuint8  *)(void *)(&__MBAR[0x0394]))

#define MCF5307_DMA3_SAR        (*(vuint32 *)(void *)(&__MBAR[0x03C0]))
#define MCF5307_DMA3_DAR        (*(vuint32 *)(void *)(&__MBAR[0x03C4]))
#define MCF5307_DMA3_DCR        (*(vuint16 *)(void *)(&__MBAR[0x03C8]))
#if (defined(CPU_MCF5307j20))
#define MCF5307_DMA3_BCR        (*(vuint32 *)(void *)(&__MBAR[0x030C]))
#else
#define MCF5307_DMA3_BCR        (*(vuint16 *)(void *)(&__MBAR[0x030C]))
#endif
#define MCF5307_DMA3_DSR        (*(vuint8  *)(void *)(&__MBAR[0x03D0]))
#define MCF5307_DMA3_DIVR       (*(vuint8  *)(void *)(&__MBAR[0x03D4]))

/* Bit level definitions and macros */
#define MCF5307_DMA_DCR_INT         (0x8000)
#define MCF5307_DMA_DCR_EEXT        (0x4000)
#define MCF5307_DMA_DCR_CS          (0x2000)
#define MCF5307_DMA_DCR_AA          (0x1000)
#define MCF5307_DMA_DCR_BWC_DMA     (0x0000)
#define MCF5307_DMA_DCR_BWC_512     (0x0200)
#define MCF5307_DMA_DCR_BWC_1024    (0x0400)
#define MCF5307_DMA_DCR_BWC_2048    (0x0600)
#define MCF5307_DMA_DCR_BWC_4096    (0x0800)
#define MCF5307_DMA_DCR_BWC_8192    (0x0a00)
#define MCF5307_DMA_DCR_BWC_16384   (0x0c00)
#define MCF5307_DMA_DCR_BWC_32768   (0x0e00)
#define MCF5307_DMA_DCR_SAA         (0x0100)
#define MCF5307_DMA_DCR_SRW         (0x0080)
#define MCF5307_DMA_DCR_SINC        (0x0040)
#define MCF5307_DMA_DCR_SSIZE_LONG  (0x0000)
#define MCF5307_DMA_DCR_SSIZE_BYTE  (0x0010)
#define MCF5307_DMA_DCR_SSIZE_WORD  (0x0020)
#define MCF5307_DMA_DCR_SSIZE_LINE  (0x0030)
#define MCF5307_DMA_DCR_DINC        (0x0008)
#define MCF5307_DMA_DCR_DSIZE_LONG  (0x0000)
#define MCF5307_DMA_DCR_DSIZE_BYTE  (0x0002)
#define MCF5307_DMA_DCR_DSIZE_WORD  (0x0004)
#define MCF5307_DMA_DCR_START       (0x0001)

#define MCF5307_DMA_DSR_CE          (0x40)  
#define MCF5307_DMA_DSR_BES         (0x20)  
#define MCF5307_DMA_DSR_BED         (0x10)  
#define MCF5307_DMA_DSR_REQ         (0x04)  
#define MCF5307_DMA_DSR_BSY         (0x02)  
#define MCF5307_DMA_DSR_DONE        (0x01)  

/***********************************************************************/

#endif  /* _CPU_MCF5307_H */