📄 mcf5307.h
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#define MCF5307_CS_CSMR_MASK_64K (0x00000000)
#define MCF5307_CS_CSMR_CPU (0x00000020)
#define MCF5307_CS_CSAR(a) (uint16)(((a)&0xFFFF0000)>>16)
#define MCF5307_CS_CSBARx(a) (uint8)(((a)&0xFF000000)>>24)
#define MCF5307_CS_CSMR_WP (0x00000100)
#define MCF5307_CS_CSMR_AM (0x00000040)
#define MCF5307_CS_CSMR_SC (0x00000010)
#define MCF5307_CS_CSMR_SD (0x00000008)
#define MCF5307_CS_CSMR_UC (0x00000004)
#define MCF5307_CS_CSMR_UD (0x00000002)
#define MCF5307_CS_CSMR_V (0x00000001)
#define MCF5307_CS_CSCR_WS(a) (((a)&0x0F)<<10)
#define MCF5307_CS_CSCR_AA (0x0100)
#define MCF5307_CS_CSCR_PS_8 (0x0040)
#define MCF5307_CS_CSCR_PS_16 (0x0080)
#define MCF5307_CS_CSCR_PS_32 (0x0000)
#define MCF5307_CS_CSCR_BEM (0x0020)
#define MCF5307_CS_CSCR_BSTR (0x0010)
#define MCF5307_CS_CSCR_BSTW (0x0008)
/**********************************************************************/
/* Parallel Port (General Purpose I/O) Module, PP */
/**********************************************************************/
/* Read/Write access macros for general use */
#define MCF5307_PP_PADDR (*(vuint16 *)(void *)(&__MBAR[0x0244]))
#define MCF5307_PP_PADAT (*(vuint16 *)(void *)(&__MBAR[0x0248]))
/* Bit level definitions and macros */
#define MCF5307_PP_PADDR_15 (0x8000)
#define MCF5307_PP_PADDR_14 (0x4000)
#define MCF5307_PP_PADDR_13 (0x2000)
#define MCF5307_PP_PADDR_12 (0x1000)
#define MCF5307_PP_PADDR_11 (0x0800)
#define MCF5307_PP_PADDR_10 (0x0400)
#define MCF5307_PP_PADDR_9 (0x0200)
#define MCF5307_PP_PADDR_8 (0x0100)
#define MCF5307_PP_PADDR_7 (0x0080)
#define MCF5307_PP_PADDR_6 (0x0040)
#define MCF5307_PP_PADDR_5 (0x0020)
#define MCF5307_PP_PADDR_4 (0x0010)
#define MCF5307_PP_PADDR_3 (0x0008)
#define MCF5307_PP_PADDR_2 (0x0004)
#define MCF5307_PP_PADDR_1 (0x0002)
#define MCF5307_PP_PADDR_0 (0x0001)
#define MCF5307_PP_PADAT_15 (0x8000)
#define MCF5307_PP_PADAT_14 (0x4000)
#define MCF5307_PP_PADAT_13 (0x2000)
#define MCF5307_PP_PADAT_12 (0x1000)
#define MCF5307_PP_PADAT_11 (0x0800)
#define MCF5307_PP_PADAT_10 (0x0400)
#define MCF5307_PP_PADAT_9 (0x0200)
#define MCF5307_PP_PADAT_8 (0x0100)
#define MCF5307_PP_PADAT_7 (0x0080)
#define MCF5307_PP_PADAT_6 (0x0040)
#define MCF5307_PP_PADAT_5 (0x0020)
#define MCF5307_PP_PADAT_4 (0x0010)
#define MCF5307_PP_PADAT_3 (0x0008)
#define MCF5307_PP_PADAT_2 (0x0004)
#define MCF5307_PP_PADAT_1 (0x0002)
#define MCF5307_PP_PADAT_0 (0x0001)
/**********************************************************************/
/* DRAM Controller Module, DRAMC */
/**********************************************************************/
/* Read/Write access macros for general use */
#define MCF5307_DRAMC_DCR (*(vuint16 *)(void *)(&__MBAR[0x0100]))
#define MCF5307_DRAMC_DACR0 (*(vuint32 *)(void *)(&__MBAR[0x0108]))
#define MCF5307_DRAMC_DMR0 (*(vuint32 *)(void *)(&__MBAR[0x010C]))
#define MCF5307_DRAMC_DACR1 (*(vuint32 *)(void *)(&__MBAR[0x0110]))
#define MCF5307_DRAMC_DMR1 (*(vuint32 *)(void *)(&__MBAR[0x0114]))
/* Bit level definitions and macros */
#define MCF5307_DRAMC_DCR_SO (0x8000)
#define MCF5307_DRAMC_DCR_NAM (0x2000)
#define MCF5307_DRAMC_DCR_RC(a) ((a)&0x01FF)
#define MCF5307_DRAMC_DACR_BASE(a) ((a)&0xFFFC0000)
#define MCF5307_DRAMC_DACR_RE (0x00008000)
#define MCF5307_DRAMC_DACR_PS_32 (0x00000000)
#define MCF5307_DRAMC_DACR_PS_8 (0x00000010)
#define MCF5307_DRAMC_DACR_PS_16 (0x00000020)
#define MCF5307_DRAMC_DCMR_MASK_4G (0xFFFC0000)
#define MCF5307_DRAMC_DCMR_MASK_2G (0x7FFC0000)
#define MCF5307_DRAMC_DCMR_MASK_1G (0x3FFC0000)
#define MCF5307_DRAMC_DCMR_MASK_1024M (0x3FFC0000)
#define MCF5307_DRAMC_DCMR_MASK_512M (0x1FFC0000)
#define MCF5307_DRAMC_DCMR_MASK_256M (0x0FFC0000)
#define MCF5307_DRAMC_DCMR_MASK_128M (0x07FC0000)
#define MCF5307_DRAMC_DCMR_MASK_64M (0x03FC0000)
#define MCF5307_DRAMC_DCMR_MASK_32M (0x01FC0000)
#define MCF5307_DRAMC_DCMR_MASK_16M (0x00FC0000)
#define MCF5307_DRAMC_DCMR_MASK_8M (0x007C0000)
#define MCF5307_DRAMC_DCMR_MASK_4M (0x003C0000)
#define MCF5307_DRAMC_DCMR_MASK_2M (0x001C0000)
#define MCF5307_DRAMC_DCMR_MASK_1M (0x000C0000)
#define MCF5307_DRAMC_DCMR_MASK_1024K (0x00040000)
#define MCF5307_DRAMC_DCMR_MASK_512K (0x00000000)
#define MCF5307_DRAMC_DCMR_WP (0x00000100)
#define MCF5307_DRAMC_DCMR_CPU (0x00000040)
#define MCF5307_DRAMC_DCMR_AM (0x00000020)
#define MCF5307_DRAMC_DCMR_SC (0x00000010)
#define MCF5307_DRAMC_DCMR_SD (0x00000008)
#define MCF5307_DRAMC_DCMR_UC (0x00000004)
#define MCF5307_DRAMC_DCMR_UD (0x00000002)
#define MCF5307_DRAMC_DCMR_V (0x00000001)
#define MCF5307_DRAMC_DCR_RRA_2 (0x0000)
#define MCF5307_DRAMC_DCR_RRA_3 (0x0800)
#define MCF5307_DRAMC_DCR_RRA_4 (0x1000)
#define MCF5307_DRAMC_DCR_RRA_5 (0x1800)
#define MCF5307_DRAMC_DCR_RRP_1 (0x0000)
#define MCF5307_DRAMC_DCR_RRP_2 (0x0200)
#define MCF5307_DRAMC_DCR_RRP_3 (0x0400)
#define MCF5307_DRAMC_DCR_RRP_4 (0x0600)
#define MCF5307_DRAMC_DACR_CAS_1 (0x00000000)
#define MCF5307_DRAMC_DACR_CAS_2 (0x00001000)
#define MCF5307_DRAMC_DACR_CAS_3 (0x00002000)
#define MCF5307_DRAMC_DACR_CAS_4 (0x00003000)
#define MCF5307_DRAMC_DACR_RP_1 (0x00000000)
#define MCF5307_DRAMC_DACR_RP_2 (0x00000400)
#define MCF5307_DRAMC_DACR_RP_3 (0x00000800)
#define MCF5307_DRAMC_DACR_RP_4 (0x00000C00)
#define MCF5307_DRAMC_DACR_RNCN (0x00000200)
#define MCF5307_DRAMC_DACR_RCD_1 (0x00000000)
#define MCF5307_DRAMC_DACR_RCD_2 (0x00000100)
#define MCF5307_DRAMC_DACR_EDO (0x00000040)
#define MCF5307_DRAMC_DACR_PM_OFF (0x00000000)
#define MCF5307_DRAMC_DACR_PM_BURST (0x00000004)
#define MCF5307_DRAMC_DACR_PM_ON (0x0000000C)
#define MCF5307_DRAMC_DCR_COC (0x1000)
#define MCF5307_DRAMC_DCR_IS (0x0800)
#define MCF5307_DRAMC_DCR_RTIM_3 (0x0000)
#define MCF5307_DRAMC_DCR_RTIM_6 (0x0200)
#define MCF5307_DRAMC_DCR_RTIM_9 (0x0400)
#define MCF5307_DRAMC_DACR_CASL_1 (0x00000000)
#define MCF5307_DRAMC_DACR_CASL_2 (0x00001000)
#define MCF5307_DRAMC_DACR_CASL_3 (0x00002000)
#define MCF5307_DRAMC_DACR_CBM(a) (((a)&0x00000007)<<8)
#define MCF5307_DRAMC_DACR_IMRS (0x00000040)
#define MCF5307_DRAMC_DACR_IP (0x00000008)
#define MCF5307_DRAMC_DACR_PM (0x00000004)
/**********************************************************************/
/* UART Module, UART */
/**********************************************************************/
/* Read/Write access macros for general use */
#define MCF5307_UART0_UMR (*(vuint8 *)(void *)(&__MBAR[0x1C0]))
#define MCF5307_UART0_USR (*(vuint8 *)(void *)(&__MBAR[0x1C4]))
#define MCF5307_UART0_UCSR (*(vuint8 *)(void *)(&__MBAR[0x1C4]))
#define MCF5307_UART0_UCR (*(vuint8 *)(void *)(&__MBAR[0x1C8]))
#define MCF5307_UART0_URB (*(vuint8 *)(void *)(&__MBAR[0x1CC]))
#define MCF5307_UART0_UTB (*(vuint8 *)(void *)(&__MBAR[0x1CC]))
#define MCF5307_UART0_UIPCR (*(vuint8 *)(void *)(&__MBAR[0x1D0]))
#define MCF5307_UART0_UACR (*(vuint8 *)(void *)(&__MBAR[0x1D0]))
#define MCF5307_UART0_UISR (*(vuint8 *)(void *)(&__MBAR[0x1D4]))
#define MCF5307_UART0_UIMR (*(vuint8 *)(void *)(&__MBAR[0x1D4]))
#define MCF5307_UART0_UBG1 (*(vuint8 *)(void *)(&__MBAR[0x1D8]))
#define MCF5307_UART0_UBG2 (*(vuint8 *)(void *)(&__MBAR[0x1DC]))
#define MCF5307_UART0_UIVR (*(vuint8 *)(void *)(&__MBAR[0x1F0]))
#define MCF5307_UART0_UIP (*(vuint8 *)(void *)(&__MBAR[0x1F4]))
#define MCF5307_UART0_UOP1 (*(vuint8 *)(void *)(&__MBAR[0x1F8]))
#define MCF5307_UART0_UOP0 (*(vuint8 *)(void *)(&__MBAR[0x1FC]))
#define MCF5307_UART1_UMR (*(vuint8 *)(void *)(&__MBAR[0x200]))
#define MCF5307_UART1_USR (*(vuint8 *)(void *)(&__MBAR[0x204]))
#define MCF5307_UART1_UCSR (*(vuint8 *)(void *)(&__MBAR[0x204]))
#define MCF5307_UART1_UCR (*(vuint8 *)(void *)(&__MBAR[0x208]))
#define MCF5307_UART1_URB (*(vuint8 *)(void *)(&__MBAR[0x20C]))
#define MCF5307_UART1_UTB (*(vuint8 *)(void *)(&__MBAR[0x20C]))
#define MCF5307_UART1_UIPCR (*(vuint8 *)(void *)(&__MBAR[0x210]))
#define MCF5307_UART1_UACR (*(vuint8 *)(void *)(&__MBAR[0x210]))
#define MCF5307_UART1_UISR (*(vuint8 *)(void *)(&__MBAR[0x214]))
#define MCF5307_UART1_UIMR (*(vuint8 *)(void *)(&__MBAR[0x214]))
#define MCF5307_UART1_UBG1 (*(vuint8 *)(void *)(&__MBAR[0x218]))
#define MCF5307_UART1_UBG2 (*(vuint8 *)(void *)(&__MBAR[0x21C]))
#define MCF5307_UART1_UIVR (*(vuint8 *)(void *)(&__MBAR[0x230]))
#define MCF5307_UART1_UIP (*(vuint8 *)(void *)(&__MBAR[0x234]))
#define MCF5307_UART1_UOP1 (*(vuint8 *)(void *)(&__MBAR[0x238]))
#define MCF5307_UART1_UOP0 (*(vuint8 *)(void *)(&__MBAR[0x23C]))
/* Bit level definitions and macros */
#define MCF5307_UART_UMR1_RXRTS (0x80)
#define MCF5307_UART_UMR1_RXIRQ (0x40)
#define MCF5307_UART_UMR1_ERR (0x20)
#define MCF5307_UART_UMR1_PM_MULTI_ADDR (0x1C)
#define MCF5307_UART_UMR1_PM_MULTI_DATA (0x18)
#define MCF5307_UART_UMR1_PM_NONE (0x10)
#define MCF5307_UART_UMR1_PM_FORCE_HI (0x0C)
#define MCF5307_UART_UMR1_PM_FORCE_LO (0x08)
#define MCF5307_UART_UMR1_PM_ODD (0x04)
#define MCF5307_UART_UMR1_PM_EVEN (0x00)
#define MCF5307_UART_UMR1_BC_5 (0x00)
#define MCF5307_UART_UMR1_BC_6 (0x01)
#define MCF5307_UART_UMR1_BC_7 (0x02)
#define MCF5307_UART_UMR1_BC_8 (0x03)
#define MCF5307_UART_UMR2_CM_NORMAL (0x00)
#define MCF5307_UART_UMR2_CM_ECHO (0x40)
#define MCF5307_UART_UMR2_CM_LOCAL_LOOP (0x80)
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