📄 mcf5407.h
字号:
#define MCF5407_SIM_IRQPAR_0 (0x20) /* IRQ[1] pin to Int IL 2, not 1 */
#define MCF5407_SIM_PLLCR_ENBSTOP (0x80) /* Enable CPU STOP Instruction */
#define MCF5407_SIM_PLLCR_PLLIPL(a) (((a)&0x07)<<4) /* PLL Wake-up IPL */
#define MCF5407_SIM_MPARK_PARK(a) (((a)&0x03)<<6) /* Default Bus Master */
#define MCF5407_SIM_MPARK_E2MCTRL (0x20) /* EBus to MBus Arbitration */
#define MCF5407_SIM_MPARK_EARBCTRL (0x10) /* SBus to EBus Arbitration */
#define MCF5407_SIM_MPARK_SHOWDATA (0x08) /* Show SBus on EBus */
#define MCF5407_SIM_MPARK_BCR24BIT (0x01) /* BCR is 24 or 16 bit register */
#define MCF5407_SIM_IPR_DMA3 (0x00020000) /* Interrupt Pending DMA3 */
#define MCF5407_SIM_IPR_DMA2 (0x00010000) /* Interrupt Pending DMA2 */
#define MCF5407_SIM_IPR_DMA1 (0x00008000) /* Interrupt Pending DMA1 */
#define MCF5407_SIM_IPR_DMA0 (0x00004000) /* Interrupt Pending DMA0 */
#define MCF5407_SIM_IPR_UART1 (0x00002000) /* Interrupt Pending UART1 */
#define MCF5407_SIM_IPR_UART0 (0x00001000) /* Interrupt Pending UART0 */
#define MCF5407_SIM_IPR_I2C (0x00000800) /* Interrupt Pending I2C */
#define MCF5407_SIM_IPR_TIMER1 (0x00000400) /* Interrupt Pending TIMER1 */
#define MCF5407_SIM_IPR_TIMER0 (0x00000200) /* Interrupt Pending TIMER0 */
#define MCF5407_SIM_IPR_SWT (0x00000100) /* Interrupt Pending SWT */
#define MCF5407_SIM_IPR_EINT7 (0x00000080) /* Interrupt Pending EINT7 */
#define MCF5407_SIM_IPR_EINT6 (0x00000040) /* Interrupt Pending EINT6 */
#define MCF5407_SIM_IPR_EINT5 (0x00000020) /* Interrupt Pending EINT5 */
#define MCF5407_SIM_IPR_EINT4 (0x00000010) /* Interrupt Pending EINT4 */
#define MCF5407_SIM_IPR_EINT3 (0x00000008) /* Interrupt Pending EINT3 */
#define MCF5407_SIM_IPR_EINT2 (0x00000004) /* Interrupt Pending EINT2 */
#define MCF5407_SIM_IPR_EINT1 (0x00000002) /* Interrupt Pending EINT1 */
#define MCF5407_SIM_IMR_DMA3 (0x00020000) /* Mask DMA3 */
#define MCF5407_SIM_IMR_DMA2 (0x00010000) /* Mask DMA2 */
#define MCF5407_SIM_IMR_DMA1 (0x00008000) /* Mask DMA1 */
#define MCF5407_SIM_IMR_DMA0 (0x00004000) /* Mask DMA0 */
#define MCF5407_SIM_IMR_UART1 (0x00002000) /* Mask UART1 */
#define MCF5407_SIM_IMR_UART0 (0x00001000) /* Mask UART0 */
#define MCF5407_SIM_IMR_I2C (0x00000800) /* Mask I2C */
#define MCF5407_SIM_IMR_TIMER1 (0x00000400) /* Mask TIMER1 */
#define MCF5407_SIM_IMR_TIMER0 (0x00000200) /* Mask TIMER0 */
#define MCF5407_SIM_IMR_SWT (0x00000100) /* Mask SWT */
#define MCF5407_SIM_IMR_EINT7 (0x00000080) /* Mask EINT7 */
#define MCF5407_SIM_IMR_EINT6 (0x00000040) /* Mask EINT6 */
#define MCF5407_SIM_IMR_EINT5 (0x00000020) /* Mask EINT5 */
#define MCF5407_SIM_IMR_EINT4 (0x00000010) /* Mask EINT4 */
#define MCF5407_SIM_IMR_EINT3 (0x00000008) /* Mask EINT3 */
#define MCF5407_SIM_IMR_EINT2 (0x00000004) /* Mask EINT2 */
#define MCF5407_SIM_IMR_EINT1 (0x00000002) /* Mask EINT1 */
#define MCF5407_SIM_AVCR_AVEC7 (0x80) /* Auto Vector Ext Interrupt 7 */
#define MCF5407_SIM_AVCR_AVEC6 (0x40) /* Auto Vector Ext Interrupt 6 */
#define MCF5407_SIM_AVCR_AVEC5 (0x20) /* Auto Vector Ext Interrupt 5 */
#define MCF5407_SIM_AVCR_AVEC4 (0x10) /* Auto Vector Ext Interrupt 4 */
#define MCF5407_SIM_AVCR_AVEC3 (0x08) /* Auto Vector Ext Interrupt 3 */
#define MCF5407_SIM_AVCR_AVEC2 (0x04) /* Auto Vector Ext Interrupt 2 */
#define MCF5407_SIM_AVCR_AVEC1 (0x02) /* Auto Vector Ext Interrupt 1 */
#define MCF5407_SIM_AVCR_BLK (0x01) /* Block Address Strobe */
#define MCF5407_SIM_ICR_AVEC (0x80) /* Autovector Enable */
#define MCF5407_SIM_ICR_IL(a) (((a)&0x07)<<2) /* Interrupt Level */
#define MCF5407_SIM_ICR_IP_EXT (0x02) /* High Priority External */
#define MCF5407_SIM_ICR_IP_INT (0x01) /* High Priority Internal */
/**********************************************************************/
/* Chip-Select Module, CS */
/**********************************************************************/
/* Offsets of the registers from the MBAR */
#define MCF5407_CS_CSAR0 (0x0080)
#define MCF5407_CS_CSMR0 (0x0084)
#define MCF5407_CS_CSCR0 (0x008A)
#define MCF5407_CS_CSAR1 (0x008C)
#define MCF5407_CS_CSMR1 (0x0090)
#define MCF5407_CS_CSCR1 (0x0096)
#define MCF5407_CS_CSAR2 (0x0098)
#define MCF5407_CS_CSMR2 (0x009C)
#define MCF5407_CS_CSCR2 (0x00A2)
#define MCF5407_CS_CSAR3 (0x00A4)
#define MCF5407_CS_CSMR3 (0x00A8)
#define MCF5407_CS_CSCR3 (0x00AE)
#define MCF5407_CS_CSAR4 (0x00B0)
#define MCF5407_CS_CSMR4 (0x00B4)
#define MCF5407_CS_CSCR4 (0x00BA)
#define MCF5407_CS_CSAR5 (0x00BC)
#define MCF5407_CS_CSMR5 (0x00C0)
#define MCF5407_CS_CSCR5 (0x00C6)
#define MCF5407_CS_CSAR6 (0x00C8)
#define MCF5407_CS_CSMR6 (0x00CC)
#define MCF5407_CS_CSCR6 (0x00D2)
#define MCF5407_CS_CSAR7 (0x00D4)
#define MCF5407_CS_CSMR7 (0x00D8)
#define MCF5407_CS_CSCR7 (0x00DE)
/* Read access macros for general use */
#define MCF5407_RD_CS_CSAR0(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR0,16)
#define MCF5407_RD_CS_CSMR0(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR0,32)
#define MCF5407_RD_CS_CSCR0(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR0,16)
#define MCF5407_RD_CS_CSAR1(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR1,16)
#define MCF5407_RD_CS_CSMR1(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR1,32)
#define MCF5407_RD_CS_CSCR1(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR1,16)
#define MCF5407_RD_CS_CSAR2(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR2,16)
#define MCF5407_RD_CS_CSMR2(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR2,32)
#define MCF5407_RD_CS_CSCR2(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR2,16)
#define MCF5407_RD_CS_CSAR3(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR3,16)
#define MCF5407_RD_CS_CSMR3(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR3,32)
#define MCF5407_RD_CS_CSCR3(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR3,16)
#define MCF5407_RD_CS_CSAR4(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR4,16)
#define MCF5407_RD_CS_CSMR4(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR4,32)
#define MCF5407_RD_CS_CSCR4(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR4,16)
#define MCF5407_RD_CS_CSAR5(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR5,16)
#define MCF5407_RD_CS_CSMR5(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR5,32)
#define MCF5407_RD_CS_CSCR5(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR5,16)
#define MCF5407_RD_CS_CSAR6(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR6,16)
#define MCF5407_RD_CS_CSMR6(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR6,32)
#define MCF5407_RD_CS_CSCR6(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR6,16)
#define MCF5407_RD_CS_CSAR7(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSAR7,16)
#define MCF5407_RD_CS_CSMR7(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSMR7,32)
#define MCF5407_RD_CS_CSCR7(IMMP) Mcf5407_iord(IMMP,MCF5407_CS_CSCR7,16)
/* Write access macros for general use */
#define MCF5407_WR_CS_CSAR0(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR0,16,DATA)
#define MCF5407_WR_CS_CSMR0(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR0,32,DATA)
#define MCF5407_WR_CS_CSCR0(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR0,16,DATA)
#define MCF5407_WR_CS_CSAR1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR1,16,DATA)
#define MCF5407_WR_CS_CSMR1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR1,32,DATA)
#define MCF5407_WR_CS_CSCR1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR1,16,DATA)
#define MCF5407_WR_CS_CSAR2(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR2,16,DATA)
#define MCF5407_WR_CS_CSMR2(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR2,32,DATA)
#define MCF5407_WR_CS_CSCR2(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR2,16,DATA)
#define MCF5407_WR_CS_CSAR3(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR3,16,DATA)
#define MCF5407_WR_CS_CSMR3(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR3,32,DATA)
#define MCF5407_WR_CS_CSCR3(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR3,16,DATA)
#define MCF5407_WR_CS_CSAR4(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR4,16,DATA)
#define MCF5407_WR_CS_CSMR4(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR4,32,DATA)
#define MCF5407_WR_CS_CSCR4(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR4,16,DATA)
#define MCF5407_WR_CS_CSAR5(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR5,16,DATA)
#define MCF5407_WR_CS_CSMR5(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR5,32,DATA)
#define MCF5407_WR_CS_CSCR5(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR5,16,DATA)
#define MCF5407_WR_CS_CSAR6(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR6,16,DATA)
#define MCF5407_WR_CS_CSMR6(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR6,32,DATA)
#define MCF5407_WR_CS_CSCR6(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR6,16,DATA)
#define MCF5407_WR_CS_CSAR7(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSAR7,16,DATA)
#define MCF5407_WR_CS_CSMR7(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSMR7,32,DATA)
#define MCF5407_WR_CS_CSCR7(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_CS_CSCR7,16,DATA)
/* These definitions only exists in the CSMR for Banks 0 and 1. */
#define MCF5407_CS_CSMR_MASK_4G (0xFFFF0000) /* Set Bank to 4G */
#define MCF5407_CS_CSMR_MASK_2G (0x7FFF0000) /* Set Bank to 2G */
#define MCF5407_CS_CSMR_MASK_1G (0x3FFF0000) /* Set Bank to 1G */
#define MCF5407_CS_CSMR_MASK_1024M (0x3FFF0000) /* Set Bank to 1024M */
#define MCF5407_CS_CSMR_MASK_512M (0x1FFF0000) /* Set Bank to 512M */
#define MCF5407_CS_CSMR_MASK_256M (0x0FFF0000) /* Set Bank to 256M */
#define MCF5407_CS_CSMR_MASK_128M (0x07FF0000) /* Set Bank to 128M */
#define MCF5407_CS_CSMR_MASK_64M (0x03FF0000) /* Set Bank to 64M */
#define MCF5407_CS_CSMR_MASK_32M (0x01FF0000) /* Set Bank to 32M */
#define MCF5407_CS_CSMR_MASK_16M (0x00FF0000) /* Set Bank to 16M */
#define MCF5407_CS_CSMR_MASK_8M (0x007F0000) /* Set Bank to 8M */
#define MCF5407_CS_CSMR_MASK_4M (0x003F0000) /* Set Bank to 4M */
#define MCF5407_CS_CSMR_MASK_2M (0x001F0000) /* Set Bank to 2M */
#define MCF5407_CS_CSMR_MASK_1M (0x000F0000) /* Set Bank to 1M */
#define MCF5407_CS_CSMR_MASK_1024K (0x000F0000) /* Set Bank to 1024K */
#define MCF5407_CS_CSMR_MASK_512K (0x00070000) /* Set Bank to 512K */
#define MCF5407_CS_CSMR_MASK_256K (0x00030000) /* Set Bank to 256K */
#define MCF5407_CS_CSMR_MASK_128K (0x00010000) /* Set Bank to 128K */
#define MCF5407_CS_CSMR_MASK_64K (0x00000000) /* Set Bank to 64K */
#define MCF5407_CS_CSMR_CPU (0x00000020) /* CPU and IACK Cycle Mask */
/* The following definitions exist for all Banks 0-7 */
#define MCF5407_CS_CSAR(a) (((a)&0xFFFF0000)>>16) /* Base Address */
#define MCF5407_CS_CSBARx(a) (((a)&0xFF000000)>>24) /* Base for CS2-7 */
#define MCF5407_CS_CSMR_WP (0x00000100) /* Write Protect */
#define MCF5407_CS_CSMR_AM (0x00000040) /* Alternate Master Mask */
#define MCF5407_CS_CSMR_SC (0x00000010) /* Supervisor Code Mask */
#define MCF5407_CS_CSMR_SD (0x00000008) /* Supervisor Data Mask */
#define MCF5407_CS_CSMR_UC (0x00000004) /* User Code Mask */
#define MCF5407_CS_CSMR_UD (0x00000002) /* User Data Mask */
#define MCF5407_CS_CSMR_V (0x00000001) /* Valid Register */
#define MCF5407_CS_CSCR_WS(a) (((a)&0x0F)<<10) /* Wait States */
#define MCF5407_CS_CSCR_AA (0x0100) /* Auto Acknowledge Enable */
#define MCF5407_CS_CSCR_PS_8 (0x0040) /* Port Size: 8-bit */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -