📄 mcf5407.h
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/*
* File: src/include/cpu/coldfire/mcf5407.h
* Purpose: mcf5407 definitions
*
* Notes: This file automatically included.
*
*/
#ifndef _CPU_MCF5407_H
#define _CPU_MCF5407_H
/**********************************************************************/
/* Macro for computing address of on-chip peripheral registers */
/**********************************************************************/
#define Mcf5407_addr(IMMP,OFFSET) ((void *)&((uint8 *)IMMP)[OFFSET])
/**********************************************************************/
/* Macros for accessing the on-chip I/O resources */
/**********************************************************************/
#define Mcf5407_iord(IMMP,OFFSET,SIZE) \
*(volatile uint ## SIZE *)(Mcf5407_addr(IMMP,OFFSET))
#define Mcf5407_iowr(IMMP,OFFSET,SIZE,DATA) \
*(volatile uint ## SIZE *)(Mcf5407_addr(IMMP,OFFSET)) = (DATA)
/**********************************************************************/
/* Cache and Access Control Register routines and defintions */
/**********************************************************************/
#define MCF5407_CACR_DEC (0x80000000) /* Data Cache Enable */
#define MCF5407_CACR_DW (0x40000000) /* Data default Write-protect */
#define MCF5407_CACR_DESB (0x20000000) /* Data Enable Store Buffer */
#define MCF5407_CACR_DDPI (0x10000000) /* Data Disable CPUSHL Invalidation */
#define MCF5407_CACR_DHLCK (0x08000000) /* 1/2 Data Cache Lock Mode */
#define MCF5407_CACR_DDCM_00 (0x00000000) /* Cacheable writethrough imprecise */
#define MCF5407_CACR_DDCM_01 (0x02000000) /* Cacheable copyback */
#define MCF5407_CACR_DDCM_10 (0x04000000) /* Noncacheable precise */
#define MCF5407_CACR_DDCM_11 (0x06000000) /* Noncacheable imprecise */
#define MCF5407_CACR_DCINVA (0x01000000) /* Data Cache Invalidate All */
#define MCF5407_CACR_BEC (0x00080000) /* Branch Cache Enable */
#define MCF5407_CACR_BCINVA (0x00040000) /* Branch Cache Invalidate All */
#define MCF5407_CACR_HSDIS (0x00010000) /* Hardware Stack Disable */
#define MCF5407_CACR_IEC (0x00008000) /* Instruction Cache Enable */
#define MCF5407_CACR_IDPI (0x00001000) /* Instruction Disable CPUSHL Invalidation */
#define MCF5407_CACR_IHLCK (0x00000800) /* 1/2 Instruction Cache Lock Mode */
#define MCF5407_CACR_IDCM (0x00000400) /* Instruction default cache mode (Noncacheable) */
#define MCF5407_CACR_ICINVA (0x00000100) /* Instruction Cache Invalidate All */
#define MCF5407_ACR_BASE(a) ((a)&0xFF000000) /* Address Base */
#define MCF5407_ACR_MASK(a) (((a)&0xFF000000)>>8) /* Address Mask */
#define MCF5407_ACR_E (0x00008000) /* Enable */
#define MCF5407_ACR_S_USER (0x00000000) /* User Mode Access */
#define MCF5407_ACR_S_SUPER (0x00002000) /* Supervisor Mode Access */
#define MCF5407_ACR_S_IGNORE (0x00004000) /* Ignore Mode Access */
#define MCF5407_ACR_CM_00 (0x00000000) /* Cacheable, writethrough */
#define MCF5407_ACR_CM_01 (0x00000020) /* Cacheable, copyback */
#define MCF5407_ACR_CM_10 (0x00000040) /* Cache-Inhibited, precise */
#define MCF5407_ACR_CM_11 (0x00000060) /* Cache-Inhibited, imprecise */
#define MCF5407_ACR_WP (0x00000004) /* Write Protect */
#define MCF5407_VBR_BASE(a) ((a)&0xFFF00000) /* Vector Base Address */
#define MCF5407_RAMBAR_BASE(a) ((a)&0xFFFFF800) /* Base Address */
#define MCF5407_RAMBAR_WP (0x00000100) /* Write Protect */
#define MCF5407_RAMBAR_DI (0x00000080) /* Memory assigned to Data(0) or Instruction(1) */
#define MCF5407_RAMBAR_AS_CPU (0x00000020) /* CPU Space/Interrupt acknowledge */
#define MCF5407_RAMBAR_AS_SC (0x00000010) /* Supervisor Code */
#define MCF5407_RAMBAR_AS_SD (0x00000008) /* Supervisor Data */
#define MCF5407_RAMBAR_AS_UC (0x00000004) /* User Code */
#define MCF5407_RAMBAR_AS_UD (0x00000002) /* User Data */
#define MCF5407_RAMBAR_V (0x00000001) /* Valid */
#define MCF5407_MBAR_BASE(a) ((a)&0xFFFFF000) /* Base Address */
#define MCF5407_MBAR_WP (0x00000100) /* Write Protect */
#define MCF5407_MBAR_AM (0x00000040) /* Alternate master mask */
#define MCF5407_MBAR_CI (0x00000020) /* Mask CPU space and interrupt acknowledge cycles */
#define MCF5407_MBAR_SC (0x00000010) /* Mask Supervisor Code Space */
#define MCF5407_MBAR_SD (0x00000008) /* Mask Supervisor Data Space */
#define MCF5407_MBAR_UC (0x00000004) /* Mask User Code Space */
#define MCF5407_MBAR_UD (0x00000002) /* Mask User Data Space */
#define MCF5407_MBAR_V (0x00000001) /* Valid */
/**********************************************************************/
/* System Integration Modules, SIM */
/**********************************************************************/
/* Offsets of the registers from the MBAR */
#define MCF5407_SIM_RSR (0x0000)
#define MCF5407_SIM_SYPCR (0x0001)
#define MCF5407_SIM_SWIVR (0x0002)
#define MCF5407_SIM_SWSR (0x0003)
#define MCF5407_SIM_PAR (0x0004)
#define MCF5407_SIM_IRQPAR (0x0006)
#define MCF5407_SIM_PLLCR (0x0008)
#define MCF5407_SIM_MPARK (0x000C)
#define MCF5407_SIM_IPR (0x0040)
#define MCF5407_SIM_IMR (0x0044)
#define MCF5407_SIM_AVCR (0x004B)
#define MCF5407_SIM_ICR0 (0x004C)
#define MCF5407_SIM_ICR1 (0x004D)
#define MCF5407_SIM_ICR2 (0x004E)
#define MCF5407_SIM_ICR3 (0x004F)
#define MCF5407_SIM_ICR4 (0x0050)
#define MCF5407_SIM_ICR5 (0x0051)
#define MCF5407_SIM_ICR6 (0x0052)
#define MCF5407_SIM_ICR7 (0x0053)
#define MCF5407_SIM_ICR8 (0x0054)
#define MCF5407_SIM_ICR9 (0x0055)
#define MCF5407_SIM_ICR10 (0x0056)
#define MCF5407_SIM_ICR11 (0x0057)
/* Read access macros for general use */
#define MCF5407_RD_SIM_RSR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_RSR,8)
#define MCF5407_RD_SIM_SYPCR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_SYPCR,8)
#define MCF5407_RD_SIM_SWIVR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_SWIVR,8)
#define MCF5407_RD_SIM_PAR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_PAR,16)
#define MCF5407_RD_SIM_IRQPAR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_IRQPAR,8)
#define MCF5407_RD_SIM_PLLCR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_PLLCR,8)
#define MCF5407_RD_SIM_MPARK(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_MPARK,8)
#define MCF5407_RD_SIM_IPR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_IPR,32)
#define MCF5407_RD_SIM_IMR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_IMR,32)
#define MCF5407_RD_SIM_AVCR(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_AVCR,8)
#define MCF5407_RD_SIM_ICR0(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR0,8)
#define MCF5407_RD_SIM_ICR1(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR1,8)
#define MCF5407_RD_SIM_ICR2(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR2,8)
#define MCF5407_RD_SIM_ICR3(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR3,8)
#define MCF5407_RD_SIM_ICR4(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR4,8)
#define MCF5407_RD_SIM_ICR5(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR5,8)
#define MCF5407_RD_SIM_ICR6(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR6,8)
#define MCF5407_RD_SIM_ICR7(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR7,8)
#define MCF5407_RD_SIM_ICR8(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR8,8)
#define MCF5407_RD_SIM_ICR9(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR9,8)
#define MCF5407_RD_SIM_ICR10(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR10,8)
#define MCF5407_RD_SIM_ICR11(IMMP) Mcf5407_iord(IMMP,MCF5407_SIM_ICR11,8)
/* Write access macros for general use */
#define MCF5407_WR_SIM_RSR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_RSR,8,DATA)
#define MCF5407_WR_SIM_SYPCR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_SYPCR,8,DATA)
#define MCF5407_WR_SIM_SWIVR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_SWIVR,8,DATA)
#define MCF5407_WR_SIM_SWSR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_SWSR,8,DATA)
#define MCF5407_WR_SIM_PAR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_PAR,16,DATA)
#define MCF5407_WR_SIM_IRQPAR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_IRQPAR,8,DATA)
#define MCF5407_WR_SIM_PLLCR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_PLLCR,8,DATA)
#define MCF5407_WR_SIM_MPARK(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_MPARK,8,DATA)
#define MCF5407_WR_SIM_IPR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_IPR,32,DATA)
#define MCF5407_WR_SIM_IMR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_IMR,32,DATA)
#define MCF5407_WR_SIM_AVCR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_AVCR,8,DATA)
#define MCF5407_WR_SIM_ICR0(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR0,8,DATA)
#define MCF5407_WR_SIM_ICR1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR1,8,DATA)
#define MCF5407_WR_SIM_ICR2(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR2,8,DATA)
#define MCF5407_WR_SIM_ICR3(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR3,8,DATA)
#define MCF5407_WR_SIM_ICR4(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR4,8,DATA)
#define MCF5407_WR_SIM_ICR5(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR5,8,DATA)
#define MCF5407_WR_SIM_ICR6(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR6,8,DATA)
#define MCF5407_WR_SIM_ICR7(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR7,8,DATA)
#define MCF5407_WR_SIM_ICR8(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR8,8,DATA)
#define MCF5407_WR_SIM_ICR9(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR9,8,DATA)
#define MCF5407_WR_SIM_ICR10(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR10,8,DATA)
#define MCF5407_WR_SIM_ICR11(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_SIM_ICR11,8,DATA)
#define MCF5407_SIM_RSR_HRST (0x80) /* Hard or System Reset */
#define MCF5407_SIM_RSR_SWTR (0x20) /* Software Watchdog Timer Reset */
#define MCF5407_SIM_SYPCR_SWE (0x80) /* Software Watchdog Enable */
#define MCF5407_SIM_SYPCR_SWRI (0x40) /* SW Reset/Interrupt Select */
#define MCF5407_SIM_SYPCR_SWT_2_9 (0x00) /* SW Timeout: 2^9 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_11 (0x08) /* SW Timeout: 2^11 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_13 (0x10) /* SW Timeout: 2^13 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_15 (0x18) /* SW Timeout: 2^15 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_18 (0x20) /* SW Timeout: 2^18 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_20 (0x28) /* SW Timeout: 2^20 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_22 (0x30) /* SW Timeout: 2^22 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWT_2_24 (0x38) /* SW Timeout: 2^24 / Sys Freq */
#define MCF5407_SIM_SYPCR_SWTA (0x04) /* SW Transfer Acknowledge Enable */
#define MCF5407_SIM_SYPCR_SWTAVAL (0x02) /* SW Transfer Acknowledge Valid */
#define MCF5407_SIM_SWSR_55 (0x55) /* Write $55 to SWSR */
#define MCF5407_SIM_SWSR_AA (0xaa) /* Write $AA to SWSR */
#define MCF5407_SIM_PAR_ADDR31 (0x8000) /* Assign Pin as ADDR31 */
#define MCF5407_SIM_PAR_ADDR30 (0x4000) /* Assign Pin as ADDR30 */
#define MCF5407_SIM_PAR_ADDR29 (0x2000) /* Assign Pin as ADDR29 */
#define MCF5407_SIM_PAR_ADDR28 (0x1000) /* Assign Pin as ADDR28 */
#define MCF5407_SIM_PAR_ADDR27 (0x0800) /* Assign Pin as ADDR27 */
#define MCF5407_SIM_PAR_ADDR26 (0x0400) /* Assign Pin as ADDR26 */
#define MCF5407_SIM_PAR_ADDR25 (0x0200) /* Assign Pin as ADDR25 */
#define MCF5407_SIM_PAR_ADDR24 (0x0100) /* Assign Pin as ADDR24 */
#define MCF5407_SIM_PAR_XTIP (0x0080) /* Assign Pin as XTIP */
#define MCF5407_SIM_PAR_DREQ0 (0x0040) /* Assign Pin as DREQ0 */
#define MCF5407_SIM_PAR_DREQ1 (0x0020) /* Assign Pin as DREQ1 */
#define MCF5407_SIM_PAR_TM2 (0x0010) /* Assign Pin as TM2 */
#define MCF5407_SIM_PAR_TM1 (0x0008) /* Assign Pin as TM1 */
#define MCF5407_SIM_PAR_TM0 (0x0004) /* Assign Pin as TM0 */
#define MCF5407_SIM_PAR_TT1 (0x0002) /* Assign Pin as TT1 */
#define MCF5407_SIM_PAR_TT0 (0x0001) /* Assign Pin as TT0 */
#define MCF5407_SIM_IRQPAR_2 (0x80) /* IRQ[5] pin to Int IL 4, not 5 */
#define MCF5407_SIM_IRQPAR_1 (0x40) /* IRQ[3] pin to Int IL 6, not 3 */
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