📄 ns8390.h
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/*
* File: dev/ns8390.h
* Purpose: Definitions for the National Semiconductor NS8390
* Ethernet chipset, commonly used in NE2000-type cards.
*
* Notes:
*
* Modifications:
*/
#ifndef _DEV_NS8390_H
#define _DEV_NS8390_H
/********************************************************************/
#ifndef NS8390_CUSTOM
/*
* This macro defines the interval between registers on the device as
* seen by the CPU.
*/
#ifndef NS8390_INTERVAL
#error "Must define value for NS8390_INTERVAL"
#endif
/*
* This macros defines the offset from zero of the first register on
* the device. It is then assumed that the next register is INTERVAL
* bytes away.
*/
#ifndef NS8390_OFFSET
#error "Must define value for NS8390_OFFSET"
#endif
#endif /* NS8390_CUSTOM */
/********************************************************************/
/*
* Physical device register offsets
*/
#define NS8390_CR 0 /* Read/Write */
#define NS8390_P0_CLDA0 1 /* Read */
#define NS8390_P0_PSTART 1 /* Write */
#define NS8390_P0_CLDA1 2 /* Read */
#define NS8390_P0_PSTOP 2 /* Write */
#define NS8390_P0_BNRY 3 /* Read/Write */
#define NS8390_P0_TSR 4 /* Read */
#define NS8390_P0_TPSR 4 /* Write */
#define NS8390_P0_NCR 5 /* Read */
#define NS8390_P0_TBCR0 5 /* Write */
#define NS8390_P0_FIFO 6 /* Read */
#define NS8390_P0_TBCR1 6 /* Write */
#define NS8390_P0_ISR 7 /* Read/Write */
#define NS8390_P0_CRDA0 8 /* Read */
#define NS8390_P0_RSAR0 8 /* Write */
#define NS8390_P0_CRDA1 9 /* Read */
#define NS8390_P0_RSAR1 9 /* Write */
#define NS8390_P0_RBCR0 10 /* Read/Write */
#define NS8390_P0_RBCR1 11 /* Read/Write */
#define NS8390_P0_RSR 12 /* Read */
#define NS8390_P0_RCR 12 /* Write */
#define NS8390_P0_CNTR0 13 /* Read */
#define NS8390_P0_TCR 13 /* Write */
#define NS8390_P0_CNTR1 14 /* Read */
#define NS8390_P0_DCR 14 /* Write */
#define NS8390_P0_CNTR2 15 /* Read */
#define NS8390_P0_IMR 15 /* Write */
#define NS8390_P1_PAR0 1 /* Read/Write */
#define NS8390_P1_PAR1 2 /* Read/Write */
#define NS8390_P1_PAR2 3 /* Read/Write */
#define NS8390_P1_PAR3 4 /* Read/Write */
#define NS8390_P1_PAR4 5 /* Read/Write */
#define NS8390_P1_PAR5 6 /* Read/Write */
#define NS8390_P1_CURR 7 /* Read/Write */
#define NS8390_P1_MAR0 8 /* Read/Write */
#define NS8390_P1_MAR1 9 /* Read/Write */
#define NS8390_P1_MAR2 10 /* Read/Write */
#define NS8390_P1_MAR3 11 /* Read/Write */
#define NS8390_P1_MAR4 12 /* Read/Write */
#define NS8390_P1_MAR5 13 /* Read/Write */
#define NS8390_P1_MAR6 14 /* Read/Write */
#define NS8390_P1_MAR7 15 /* Read/Write */
#define NS8390_P2_PSTART 1 /* Read */
#define NS8390_P2_CLDA0 1 /* Write */
#define NS8390_P2_PSTOP 2 /* Read */
#define NS8390_P2_CLDA1 2 /* Write */
#define NS8390_P2_RNPP 3 /* Read/Write */
#define NS8390_P2_TPSR 4 /* Read */
#define NS8390_P2_LNPP 5 /* Read/Write */
#define NS8390_P2_ACU 6 /* Read/Write */
#define NS8390_P2_ACL 7 /* Read/Write */
#define NS8390_P2_ILSR 9 /* Read */
#define NS8390_P2_ILPDR 9 /* Write */
#define NS8390_P2_RCR 12 /* Read */
#define NS8390_P2_TCR 13 /* Read */
#define NS8390_P2_DCR 14 /* Read */
#define NS8390_P2_IMR 15 /* Read */
#define NS8390_DATAPORT 16 /* Read/Write */
/*
* Definitions of register contents
*/
#define NS8390_CR_STP (0x01)
#define NS8390_CR_STA (0x02)
#define NS8390_CR_TXP (0x04)
#define NS8390_CR_RD_RD (0x08)
#define NS8390_CR_RD_WR (0x10)
#define NS8390_CR_RD_SP (0x11)
#define NS8390_CR_RD_AB (0x20)
#define NS8390_CR_PAGE0 (0x00)
#define NS8390_CR_PAGE1 (0x40)
#define NS8390_CR_PAGE2 (0x80)
#define NS8390_CR_PAGE3 (0xC0)
#define NS8390_TCR_CRC (0x01)
#define NS8390_TCR_LOOP_NO (0x00)
#define NS8390_TCR_LOOP_I0 (0x02)
#define NS8390_TCR_LOOP_E1 (0x04)
#define NS8390_TCR_LOOP_E0 (0x06)
#define NS8390_TCR_ATD (0x08)
#define NS8390_TCR_OFST (0x10)
#define NS8390_DCR_WTS (0x01)
#define NS8390_DCR_BOS (0x02)
#define NS8390_DCR_LAS (0x04)
#define NS8390_DCR_LS (0x08)
#define NS8390_DCR_AR (0x10)
#define NS8390_DCR_FT_2B (0x00)
#define NS8390_DCR_FT_4B (0x20)
#define NS8390_DCR_FT_8B (0x40)
#define NS8390_DCR_FT_12B (0x60)
#define NS8390_DCR_FT_1W (0x00)
#define NS8390_DCR_FT_2W (0x20)
#define NS8390_DCR_FT_4W (0x40)
#define NS8390_DCR_FT_6W (0x60)
#define NS8390_RCR_SEP (0x01)
#define NS8390_RCR_AR (0x02)
#define NS8390_RCR_AB (0x04)
#define NS8390_RCR_AM (0x08)
#define NS8390_RCR_PRO (0x10)
#define NS8390_RCR_MON (0x20)
#define NS8390_ISR_PRX (0x01)
#define NS8390_ISR_PTX (0x02)
#define NS8390_ISR_RXE (0x04)
#define NS8390_ISR_TXE (0x08)
#define NS8390_ISR_OVW (0x10)
#define NS8390_ISR_CNT (0x20)
#define NS8390_ISR_RDC (0x40)
#define NS8390_ISR_RST (0x80)
#define NS8390_IMR_PRXE (0x01)
#define NS8390_IMR_PTXE (0x02)
#define NS8390_IMR_RXEE (0x04)
#define NS8390_IMR_TXEE (0x08)
#define NS8390_IMR_OVWE (0x10)
#define NS8390_IMR_CNTE (0x20)
#define NS8390_IMR_RDCE (0x40)
#define NS8390_RSR_PRX (0x01)
#define NS8390_RSR_CRC (0x02)
#define NS8390_RSR_FAE (0x04)
#define NS8390_RSR_FO (0x08)
#define NS8390_RSR_MPA (0x10)
#define NS8390_RSR_PHY (0x20)
#define NS8390_RSR_DIS (0x40)
#define NS8390_RSR_DFR (0x80)
#define NS8390_TSR_PTX (0x01)
#define NS8390_TSR_COL (0x04)
#define NS8390_TSR_ABT (0x08)
#define NS8390_TSR_CRS (0x10)
#define NS8390_TSR_FU (0x20)
#define NS8390_TSR_CDH (0x40)
#define NS8390_TSR_OWC (0x80)
/********************************************************************/
/*
* If the device is connected to the system in a "non-standard" way,
* then obtain the board-specifics.
*/
#ifdef NS8390_CUSTOM
#include "ns8390l.h"
#else
/*
* Macros for accessing the peripheral registers
*/
#define Ns8390_addr(BASE,REG) \
((void *)&((uint8 *)BASE)[(REG * NS8390_INTERVAL) + NS8390_OFFSET])
#define Ns8390_iord(BASE,REG) \
cpu_iord_8(Ns8390_addr(BASE,REG))
#define Ns8390_iowr(BASE,REG,DATA) \
cpu_iowr_8(Ns8390_addr(BASE,REG),DATA)
#define Ns8390_iord16(BASE,REG) \
cpu_iord_16(Ns8390_addr(BASE,REG))
#define Ns8390_iowr16(BASE,REG,DATA) \
cpu_iowr_16(Ns8390_addr(BASE,REG),DATA)
/* Read macros for general use */
#define NS8390_RD_CR(BASE) Ns8390_iord(BASE,NS8390_CR)
#define NS8390_RD_P0_CLDA0(BASE) Ns8390_iord(BASE,NS8390_P0_CLDA0)
#define NS8390_RD_P0_CLDA1(BASE) Ns8390_iord(BASE,NS8390_P0_CLDA1)
#define NS8390_RD_P0_BNRY(BASE) Ns8390_iord(BASE,NS8390_P0_BNRY)
#define NS8390_RD_P0_TSR(BASE) Ns8390_iord(BASE,NS8390_P0_TSR)
#define NS8390_RD_P0_NCR(BASE) Ns8390_iord(BASE,NS8390_P0_NCR)
#define NS8390_RD_P0_FIFO(BASE) Ns8390_iord(BASE,NS8390_P0_FIFO)
#define NS8390_RD_P0_ISR(BASE) Ns8390_iord(BASE,NS8390_P0_ISR)
#define NS8390_RD_P0_CRDA0(BASE) Ns8390_iord(BASE,NS8390_P0_CRDA0)
#define NS8390_RD_P0_CRDA1(BASE) Ns8390_iord(BASE,NS8390_P0_CRDA1)
#define NS8390_RD_P0_RBDR0(BASE) Ns8390_iord(BASE,NS8390_P0_RBCR0)
#define NS8390_RD_P0_RBCR1(BASE) Ns8390_iord(BASE,NS8390_P0_RBCR1)
#define NS8390_RD_P0_RSR(BASE) Ns8390_iord(BASE,NS8390_P0_RSR)
#define NS8390_RD_P0_CNTR0(BASE) Ns8390_iord(BASE,NS8390_P0_CNTR0)
#define NS8390_RD_P0_CNTR1(BASE) Ns8390_iord(BASE,NS8390_P0_CNTR1)
#define NS8390_RD_P0_CNTR2(BASE) Ns8390_iord(BASE,NS8390_P0_CNTR2)
#define NS8390_RD_P1_PAR0(BASE) Ns8390_iord(BASE,NS8390_P1_PAR0)
#define NS8390_RD_P1_PAR1(BASE) Ns8390_iord(BASE,NS8390_P1_PAR1)
#define NS8390_RD_P1_PAR2(BASE) Ns8390_iord(BASE,NS8390_P1_PAR2)
#define NS8390_RD_P1_PAR3(BASE) Ns8390_iord(BASE,NS8390_P1_PAR3)
#define NS8390_RD_P1_PAR4(BASE) Ns8390_iord(BASE,NS8390_P1_PAR4)
#define NS8390_RD_P1_PAR5(BASE) Ns8390_iord(BASE,NS8390_P1_PAR5)
#define NS8390_RD_P1_CURR(BASE) Ns8390_iord(BASE,NS8390_P1_CURR)
#define NS8390_RD_P1_MAR0(BASE) Ns8390_iord(BASE,NS8390_P1_MAR0)
#define NS8390_RD_P1_MAR1(BASE) Ns8390_iord(BASE,NS8390_P1_MAR1)
#define NS8390_RD_P1_MAR2(BASE) Ns8390_iord(BASE,NS8390_P1_MAR2)
#define NS8390_RD_P1_MAR3(BASE) Ns8390_iord(BASE,NS8390_P1_MAR3)
#define NS8390_RD_P1_MAR4(BASE) Ns8390_iord(BASE,NS8390_P1_MAR4)
#define NS8390_RD_P1_MAR5(BASE) Ns8390_iord(BASE,NS8390_P1_MAR5)
#define NS8390_RD_P1_MAR6(BASE) Ns8390_iord(BASE,NS8390_P1_MAR6)
#define NS8390_RD_P1_MAR7(BASE) Ns8390_iord(BASE,NS8390_P1_MAR7)
#define NS8390_RD_P2_PSTART(BASE) Ns8390_iord(BASE,NS8390_P2_PSTART)
#define NS8390_RD_P2_PSTOP(BASE) Ns8390_iord(BASE,NS8390_P2_PSTOP)
#define NS8390_RD_P2_RNPP(BASE) Ns8390_iord(BASE,NS8390_P2_RNPP)
#define NS8390_RD_P2_TPSR(BASE) Ns8390_iord(BASE,NS8390_P2_TPSR)
#define NS8390_RD_P2_LNPP(BASE) Ns8390_iord(BASE,NS8390_P2_LNPP)
#define NS8390_RD_P2_ACU(BASE) Ns8390_iord(BASE,NS8390_P2_ACU)
#define NS8390_RD_P2_ACL(BASE) Ns8390_iord(BASE,NS8390_P2_ACL)
#define NS8390_RD_P2_RCR(BASE) Ns8390_iord(BASE,NS8390_P2_RCR)
#define NS8390_RD_P2_TCR(BASE) Ns8390_iord(BASE,NS8390_P2_TCR)
#define NS8390_RD_P2_DCR(BASE) Ns8390_iord(BASE,NS8390_P2_DCR)
#define NS8390_RD_P2_IMR(BASE) Ns8390_iord(BASE,NS8390_P2_IMR)
#define NS8390_RD_DATA8(BASE) Ns8390_iord(BASE,NS8390_DATAPORT)
#define NS8390_RD_DATA16(BASE) Ns8390_iord16(BASE,NS8390_DATAPORT)
/* Write macros for general use */
#define NS8390_WR_CR(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_CR,DATA)
#define NS8390_WR_P0_PSTART(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_PSTART,DATA)
#define NS8390_WR_P0_PSTOP(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_PSTOP,DATA)
#define NS8390_WR_P0_BNRY(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_BNRY,DATA)
#define NS8390_WR_P0_TPSR(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_TPSR,DATA)
#define NS8390_WR_P0_TBCR0(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_TBCR0,DATA)
#define NS8390_WR_P0_TBCR1(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_TBCR1,DATA)
#define NS8390_WR_P0_ISR(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_ISR,DATA)
#define NS8390_WR_P0_RSAR0(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_RSAR0,DATA)
#define NS8390_WR_P0_RSAR1(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_RSAR1,DATA)
#define NS8390_WR_P0_RBCR0(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_RBCR0,DATA)
#define NS8390_WR_P0_RBCR1(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_RBCR1,DATA)
#define NS8390_WR_P0_RCR(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_RCR,DATA)
#define NS8390_WR_P0_TCR(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_TCR,DATA)
#define NS8390_WR_P0_DCR(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_DCR,DATA)
#define NS8390_WR_P0_IMR(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P0_IMR,DATA)
#define NS8390_WR_P1_PAR0(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_PAR0,DATA)
#define NS8390_WR_P1_PAR1(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_PAR1,DATA)
#define NS8390_WR_P1_PAR2(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_PAR2,DATA)
#define NS8390_WR_P1_PAR3(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_PAR3,DATA)
#define NS8390_WR_P1_PAR4(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_PAR4,DATA)
#define NS8390_WR_P1_PAR5(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_PAR5,DATA)
#define NS8390_WR_P1_CURR(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_CURR,DATA)
#define NS8390_WR_P1_MAR0(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_MAR0,DATA)
#define NS8390_WR_P1_MAR1(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_MAR1,DATA)
#define NS8390_WR_P1_MAR2(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_MAR2,DATA)
#define NS8390_WR_P1_MAR3(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_MAR3,DATA)
#define NS8390_WR_P1_MAR4(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_MAR4,DATA)
#define NS8390_WR_P1_MAR5(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_MAR5,DATA)
#define NS8390_WR_P1_MAR6(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_MAR6,DATA)
#define NS8390_WR_P1_MAR7(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P1_MAR7,DATA)
#define NS8390_WR_P2_CLDA0(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P2_CLDA0,DATA)
#define NS8390_WR_P2_CLDA1(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P2_CLDA1,DATA)
#define NS8390_WR_P2_RNPP(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P2_RNPP,DATA)
#define NS8390_WR_P2_LNPP(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P2_LNPP,DATA)
#define NS8390_WR_P2_ACU(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P2_ACU,DATA)
#define NS8390_WR_P2_ACL(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_P2_ACL,DATA)
#define NS8390_WR_DATA8(BASE,DATA) \
Ns8390_iowr(BASE,NS8390_DATAPORT,DATA)
#define NS8390_WR_DATA16(BASE,DATA) \
Ns8390_iowr16(BASE,NS8390_DATAPORT,DATA)
#endif /* NS8390_CUSTOM */
/*
* Fake out a typedef with void, ie NS8390 * == void *
*/
#define NS8390 void
/********************************************************************/
#endif /* _DEV_NS8390_H */
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