mc68681.h

motorola 针对coldfire 5275 评估板的Dbug bootloader源程序

/*
 * File:        dev/mc68681.h
 * Purpose:     Defintions for the MC68681 DUART.
 *
 * Notes:       Macros in lower caps are meant to be private to this
 *              header file.  Macros in all caps are for global use.
 *
 *
 * Modifications:
 *
 */

#ifndef _DEV_MC68681_H
#define _DEV_MC68681_H

/********************************************************************/

#ifndef MC68681_CUSTOM

/*
 * This macros defines the interval between registers on the device.
 */
#ifndef MC68681_INTERVAL
#error "Must define value for MC68681_INTERVAL"
#endif

/*
 * This macros defines the offset from zero of the first register on
 * the device.  It is then assumed that the next register is INTERVAL
 * bytes away.
 */
#ifndef MC68681_OFFSET
#error "Must define value for MC68681_OFFSET"
#endif

#endif /* MC68681_CUSTOM */

/********************************************************************/

/*
 * Physical device register offsets
 */
#define MC68681_CH1_MR  0
#define MC68681_CH1_SR  1
#define MC68681_CH1_CSR 1
#define MC68681_CH1_CR  2
#define MC68681_CH1_BR  3
#define MC68681_IPCR    4
#define MC68681_ACR     4
#define MC68681_ISR     5
#define MC68681_IMR     5
#define MC68681_CUR     6
#define MC68681_CTUR    6
#define MC68681_CLR     7
#define MC68681_CTLR    7
#define MC68681_CH2_MR  8
#define MC68681_CH2_SR  9
#define MC68681_CH2_CSR 9
#define MC68681_CH2_CR  10
#define MC68681_CH2_BR  11
#define MC68681_IVR     12
#define MC68681_OPCR    13

/*
 * Definitions of register contents
 */

/* Definitions for the Mode Register 1 A and B */
#define MC68681_MR1_RXRTS_ENABLE            (0x80)
#define MC68681_MR1_RXIRQ_FFULL             (0x40)
#define MC68681_MR1_ERR_BLOCK               (0x20)
#define MC68681_MR1_PARITY_MULTIDROP        (0x18)
#define MC68681_MR1_PARITY_NONE             (0x10)
#define MC68681_MR1_PARITY_FORCE            (0x08)
#define MC68681_MR1_PARITY_ODD              (0x04)
#define MC68681_MR1_PARITY_HIGH             (0x04)
#define MC68681_MR1_PARITY_ADDR             (0x04)
#define MC68681_MR1_BITS_8                  (0x03)
#define MC68681_MR1_BITS_7                  (0x02)
#define MC68681_MR1_BITS_6                  (0x01)
#define MC68681_MR1_BITS_5                  (0x00)

/* Definitions for the Mode Register 2 A and B */
#define MC68681_MR2_REMOTE_LOOPBACK         (0xC0)
#define MC68681_MR2_LOCAL_LOOPBACK          (0x80)
#define MC68681_MR2_AUTOMATIC_ECHO          (0x40)
#define MC68681_MR2_TX_RTS_ENABLED          (0x20)
#define MC68681_MR2_TX_CTS_ENABLED          (0x10)
#define MC68681_MR2_STOP_BITS_1             (0x07)
#define MC68681_MR2_STOP_BITS_15            (0x08)
#define MC68681_MR2_STOP_BITS_2             (0x0F)

/* Definitions for the Command Registers A and B */
#define MC68681_CR_NO_ACTION                (0x00)
#define MC68681_CR_STOP_BREAK               (0x70)
#define MC68681_CR_START_BREAK              (0x60)
#define MC68681_CR_RESET_BKCHGINT           (0x50)
#define MC68681_CR_RESET_ERROR              (0x40)
#define MC68681_CR_RESET_TX                 (0x30)
#define MC68681_CR_RESET_RX                 (0x20)
#define MC68681_CR_RESET_MR                 (0x10)
#define MC68681_CR_TX_DISABLED              (0x08)
#define MC68681_CR_TX_ENABLED               (0x04)
#define MC68681_CR_RX_DISABLED              (0x02)
#define MC68681_CR_RX_ENABLED               (0x01)

/* Definitions for the Status Registers A and B */
#define MC68681_SR_RX_BREAK                 (0x80)
#define MC68681_SR_FRAME_ERR                (0x40)
#define MC68681_SR_PARITY_ERR               (0x20)
#define MC68681_SR_OVERRUN_ERR              (0x10)
#define MC68681_SR_TXEMT                    (0X08)
#define MC68681_SR_TXRDY                    (0X04)
#define MC68681_SR_FFULL                    (0X02)
#define MC68681_SR_RXRDY                    (0X01)

/* Definitions for the Interrupt Mask and Status Registers */
#define MC68681_IR_IPC_IRQ                  (0X80)
#define MC68681_IR_DELTA_BREAK_B_IRQ        (0x40)
#define MC68681_IR_RXRDY_B_IRQ              (0x20)
#define MC68681_IR_TXRDY_B_IRQ              (0x10)
#define MC68681_IR_CNTR_RDY_IRQ             (0x08)
#define MC68681_IR_DELTA_BREAK_A_IRQ        (0x04)
#define MC68681_IR_RXRDY_A_IRQ              (0x02)
#define MC68681_IR_TXRDY_A_IRQ              (0x01)
#define MC68681_IR_NO_INTERRUPTS            (0x00)

/* Definitions for the Auxiliary Control Register */
#define MC68681_ACR_BRG_SET_1               (0x00)
#define MC68681_ACR_BRG_SET_2               (0x80)

/* Definitions for the Auxiliary Control Register */
#define MC68681_CSR_9600_BPS                (0xBB)
#define MC68681_CSR_19200_BPS               (0xCC)

/********************************************************************/

/*
 * If the device is connected to the system in a "non-standard" way,
 * then obtain the board-specifics.
 */
#ifdef MC68681_CUSTOM
#include MC68681_CUSTOM /* Local MC68681 definitions */
#else

/*
 * Macros for accessing the peripheral registers
 */
#define Mc68681_addr(BASE,REG)      \
    ((void *)&((uint8 *)BASE)[(REG * MC68681_INTERVAL) + MC68681_OFFSET])

#define Mc68681_iord(BASE,REG)      \
    cpu_iord_8(Mc68681_addr(BASE,REG))

#define Mc68681_iowr(BASE,REG,DATA) \
    cpu_iowr_8(Mc68681_addr(BASE,REG),DATA)

#define MC68681_RD_CH1_MR(BASE)         Mc68681_iord(BASE,MC68681_CH1_MR)
#define MC68681_RD_CH1_SR(BASE)         Mc68681_iord(BASE,MC68681_CH1_SR)
#define MC68681_RD_CH1_CR(BASE)         Mc68681_iord(BASE,MC68681_CH1_CR)
#define MC68681_RD_CH1_BR(BASE)         Mc68681_iord(BASE,MC68681_CH1_BR)
#define MC68681_RD_IPCR(BASE)           Mc68681_iord(BASE,MC68681_IPCR)
#define MC68681_RD_ISR(BASE)            Mc68681_iord(BASE,MC68681_ISR)
#define MC68681_RD_CUR(BASE)            Mc68681_iord(BASE,MC68681_CUR)
#define MC68681_RD_CLR(BASE)            Mc68681_iord(BASE,MC68681_CLR)
#define MC68681_RD_CH2_MR(BASE)         Mc68681_iord(BASE,MC68681_CH2_MR)
#define MC68681_RD_CH2_SR(BASE)         Mc68681_iord(BASE,MC68681_CH2_SR)
#define MC68681_RD_CH2_CR(BASE)         Mc68681_iord(BASE,MC68681_CH2_CR)
#define MC68681_RD_CH2_BR(BASE)         Mc68681_iord(BASE,MC68681_CH2_BR)
#define MC68681_RD_IVR(BASE)            Mc68681_iord(BASE,MC68681_IVR)

#define MC68681_WR_CH1_MR(BASE,DATA)    Mc68681_iowr(BASE,MC68681_CH1_MR,DATA)
#define MC68681_WR_CH1_CSR(BASE,DATA)   Mc68681_iowr(BASE,MC68681_CH1_CSR,DATA)
#define MC68681_WR_CH1_CR(BASE,DATA)    Mc68681_iowr(BASE,MC68681_CH1_CR,DATA)
#define MC68681_WR_CH1_BR(BASE,DATA)    Mc68681_iowr(BASE,MC68681_CH1_BR,DATA)
#define MC68681_WR_ACR(BASE,DATA)       Mc68681_iowr(BASE,MC68681_ACR,DATA)
#define MC68681_WR_IMR(BASE,DATA)       Mc68681_iowr(BASE,MC68681_IMR,DATA)
#define MC68681_WR_CTUR(BASE,DATA)      Mc68681_iowr(BASE,MC68681_CTUR,DATA)
#define MC68681_WR_CTLR(BASE,DATA)      Mc68681_iowr(BASE,MC68681_CTLR,DATA)
#define MC68681_WR_CH2_MR(BASE,DATA)    Mc68681_iowr(BASE,MC68681_CH2_MR,DATA)
#define MC68681_WR_CH2_CSR(BASE,DATA)   Mc68681_iowr(BASE,MC68681_CH2_CSR,DATA)
#define MC68681_WR_CH2_CR(BASE,DATA)    Mc68681_iowr(BASE,MC68681_CH2_CR,DATA)
#define MC68681_WR_CH2_BR(BASE,DATA)    Mc68681_iowr(BASE,MC68681_CH2_BR,DATA)
#define MC68681_WR_IVR(BASE,DATA)       Mc68681_iowr(BASE,MC68681_IVR,DATA)
#define MC68681_WR_OPCR(BASE,DATA)      Mc68681_iowr(BASE,MC68681_OPCR,DATA)

#endif /* MC68681_CUSTOM */

/*
 * Fake out a typedef with void, ie (MC68681 *) is really (void *)
 */
#define MC68681 void

/********************************************************************/

#endif /*  _DEV_MC68681_H */