lan91c111.h

motorola 针对coldfire 5275 评估板的Dbug bootloader源程序

#ifndef _LAN91C111_H_
#define _LAN91C111_H_

int     lan91c111_handler (void *, NIF *);
int     lan91c111_init (NIF *, int);

/* To print out debug info, LAN91C111_DEBUG > 0  */
#define LAN91C111_DEBUG     1

/* Define the Phy address. For the internal Phy it defaults to "0" */
#define PHYADDR             0x0000

/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */

#define SMC_IO_EXTENT   16  

/* The switcharoo macro :) */
#define UBLBSWTICH(x)   (((x & 0xFF00)>>8)|((x & 0x00FF)<<8))

/*---------------------------------------------------------------
 .  
 . A description of the SMSC registers is probably in order here,
 . although for details, the SMC datasheet is invaluable.  
 . 
 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
 . are accessed by writing a number into the BANK_SELECT register
 . ( I also use a SMC_SELECT_BANK macro for this ).
 . 
 . The banks are configured so that for most purposes, bank 2 is all
 . that is needed for simple run time tasks.  
 -----------------------------------------------------------------------*/

/*
 . Bank Select Register: 
 .
 .      yyyy yyyy 0000 00xx  
 .      xx      = bank number
 .      yyyy yyyy   = 0x33, for identification purposes.
*/
#define LAN91C111_BANK_SELECT       14

/************************************************************************************************************/
/* BANK 0 - Transmit Control Register */
/*BigEndian OK */
#define LAN91C111_TCR           (*(vuint16  *)(void *)(&__ETHERNET[0x00]))  // Transmit Control Register

/* Transmit Control Register Bit Definitions */
#define LAN91C111_TCR_ENABLE    0x0100  // When 1 we can transmit
#define LAN91C111_TCR_LOOP      0x0200  // Controls output pin LBK
#define LAN91C111_TCR_FORCOL    0x0400  // When 1 will force a collision
#define LAN91C111_TCR_PAD_EN    0x8000  // When 1 will pad tx frames < 64 bytes w/0
#define LAN91C111_TCR_NOCRC     0x0001  // When 1 will not append CRC to tx frames
#define LAN91C111_TCR_MON_CSN   0x0004  // When 1 tx monitors carrier
#define LAN91C111_TCR_FDUPLX    0x0008  // When 1 enables full duplex operation
#define LAN91C111_TCR_STP_SQET  0x0010  // When 1 stops tx if Signal Quality Error
#define LAN91C111_TCR_EPH_LOOP  0x0020  // When 1 enables EPH block loopback
#define LAN91C111_TCR_SWFDUP    0x0080  // When 1 enables Switched Full Duplex mode

#define LAN91C111_TCR_CLEAR     0x0000  // do NOTHING 
#define LAN91C111_TCR_DEFAULT   LAN91C111_TCR_ENABLE 

/************************************************************************************************************/
/* BANK 0 - EPH Status Register */
/*BigEndian OK */
#define LAN91C111_EPHSR             (*(vuint16  *)(void *)(&__ETHERNET[0x02]))

/* EPH Status Register Bit Definitions */
#define LAN91C111_EPHSR_TX_SUC      0x0100  // Last TX was successful
#define LAN91C111_EPHSR_SNGL_COL    0x0200  // Single collision detected for last tx
#define LAN91C111_EPHSR_MUL_COL     0x0400  // Multiple collisions detected for last tx
#define LAN91C111_EPHSR_LTX_MULT    0x0800  // Last tx was a multicast
#define LAN91C111_EPHSR_16COL       0x1000  // 16 Collisions Reached
#define LAN91C111_EPHSR_SQET        0x2000  // Signal Quality Error Test
#define LAN91C111_EPHSR_LTXBRD      0x4000  // Last tx was a broadcast
#define LAN91C111_EPHSR_TXDEFR      0x8000  // Transmit Deferred
#define LAN91C111_EPHSR_LATCOL      0x0002  // Late collision detected on last tx
#define LAN91C111_EPHSRS_LOSTCARR   0x0004  // Lost Carrier Sense
#define LAN91C111_EPHSR_EXC_DEF     0x0008  // Excessive Deferral
#define LAN91C111_EPHSR_CTR_ROL     0x0010  // Counter Roll Over indication
#define LAN91C111_EPHSR_LINK_OK     0x0040  // Driven by inverted value of nLNK pin
#define LAN91C111_EPHSR_TXUNRN      0x0080  // Tx Underrun

/************************************************************************************************************/
/* BANK 0 - Receive Control Register */
/*BigEndian OK */
#define LAN91C111_RCR               (*(vuint16  *)(void *)(&__ETHERNET[0x04]))

/* Receive Control Register Bit Definitions */
#define LAN91C111_RCR_RX_ABORT      0x0100  // Set if a rx frame was aborted
#define LAN91C111_RCR_PRMS          0x0200  // Enable promiscuous mode
#define LAN91C111_RCR_ALMUL         0x0400  // When set accepts all multicast frames
#define LAN91C111_RCR_RXEN          0x0001  // IFF this is set, we can receive packets
#define LAN91C111_RCR_STRIP_CRC     0x0002  // When set strips CRC from rx packets
#define LAN91C111_RCR_ABORT_ENB     0x0002  // When set will abort rx on collision 
#define LAN91C111_RCR_FILT_CAR      0x0004  // When set filters leading 12 bit s of carrier
#define LAN91C111_RCR_SOFTRST       0x0080  // resets the chip

/* the normal settings for the RCR register : */
#define LAN91C111_RCR_DEFAULT       (LAN91C111_RCR_STRIP_CRC | LAN91C111_RCR_RXEN)
#define LAN91C111_RCR_CLEAR         0x0         // set it to a base state
/************************************************************************************************************/
/* BANK 0 - Counter Register */
#define LAN91C111_COUNTER           (*(vuint16  *)(void *)(&__ETHERNET[0x06]))

/************************************************************************************************************/
/* BANK 0 - Memory Information Register*/
#define LAN91C111_MIR               (*(vuint16  *)(void *)(&__ETHERNET[0x08]))

/************************************************************************************************************/
/* BANK 0 - Receive/Phy Control Register */
/*BigEndian OK */
#define LAN91C111_RPC               (*(vuint16  *)(void *)(&__ETHERNET[0x0A]))

/* Receive/Phy Control Register Bit Definitions */
#define LAN91C111_RPC_SPEED         0x0020  // When 1 PHY is in 100Mbps mode.
#define LAN91C111_RPC_DPLX          0x0010  // When 1 PHY is in Full-Duplex Mode
#define LAN91C111_RPC_ANEG          0x0008  // When 1 PHY is in Auto-Negotiate Mode
#define LAN91C111_RPC_LSXA_SHFT     0x000D  // Bits to shift LS2A,LS1A,LS0A to lsb
#define LAN91C111_RPC_LSXB_SHFT     0x000A  // Bits to get LS2B,LS1B,LS0B to lsb
#define LAN91C111_RPC_LED_100_10    (0x00)  // LED = 100Mbps OR's with 10Mbps link detect
#define LAN91C111_RPC_LED_RES       (0x01)  // LED = Reserved
#define LAN91C111_RPC_LED_10        (0x02)  // LED = 10Mbps link detect
#define LAN91C111_RPC_LED_FD        (0x03)  // LED = Full Duplex Mode
#define LAN91C111_RPC_LED_TX_RX     (0x04)  // LED = TX or RX packet occurred
#define LAN91C111_RPC_LED_100       (0x05)  // LED = 100Mbps link dectect
#define LAN91C111_RPC_LED_TX        (0x06)  // LED = TX packet occurred
#define LAN91C111_RPC_LED_RX        (0x07)  // LED = RX packet occurred
#define LAN91C111_RPC_DEFAULT       (LAN91C111_RPC_ANEG | (LAN91C111_RPC_LED_100_10 << LAN91C111_RPC_LSXA_SHFT) | (LAN91C111_RPC_LED_TX_RX << LAN91C111_RPC_LSXB_SHFT) | LAN91C111_RPC_SPEED | LAN91C111_RPC_DPLX)
//#define LAN91C111_RPC_DEFAULT     (LAN91C111_RPC_ANEG | (LAN91C111_RPC_LED_TX << LAN91C111_RPC_LSXA_SHFT) | (LAN91C111_RPC_LED_RX << LAN91C111_RPC_LSXB_SHFT) | LAN91C111_RPC_SPEED | LAN91C111_RPC_DPLX)
#define LAN91C111_RPC_10MBPS        ((LAN91C111_RPC_LED_TX << LAN91C111_RPC_LSXA_SHFT) | (LAN91C111_RPC_LED_RX << LAN91C111_RPC_LSXB_SHFT) | LAN91C111_RPC_DPLX)
/************************************************************************************************************/
/* BANK 0 0x000C is reserved */

/************************************************************************************************************/
/* ALL BANKS - Bank Select Register */
/*BigEndian OK */
#define LAN91C111_BSR               (*(vuint16  *)(void *)(&__ETHERNET[0x0E]))

/* Bank Select Register Bit Definitions */
#define LAN91C111_BSR_BANK0                 0x0000
#define LAN91C111_BSR_BANK1                 0x0100
#define LAN91C111_BSR_BANK2                 0x0200
#define LAN91C111_BSR_BANK3                 0x0300

/************************************************************************************************************/
/* BANK 1 - Configuration Reg */
/*BigEndian OK */
#define LAN91C111_CFGR                      (*(vuint16  *)(void *)(&__ETHERNET[0x00]))

/* Bank Select Register Bit Definitions */
#define LAN91C111_CFGR_EXT_PHY              0x0002  // 1=external MII, 0=internal Phy
#define LAN91C111_CFGR_GPCNTRL              0x0004  // Inverse value drives pin nCNTRL
#define LAN91C111_CFGR_NO_WAIT              0x0010  // When 1 no extra wait states on ISA bus
#define LAN91C111_CFGR_EPH_POWER_EN         0x0080  // When 0 EPH is placed into low power mode.

// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
#define LAN91C111_CFGR_DEFAULT              (LAN91C111_CFGR_EPH_POWER_EN)

/************************************************************************************************************/
/* BANK 1 - Base Address Register */
#define LAN91C111_BAR                       (*(vuint16  *)(void *)(&__ETHERNET[0x02]))

/************************************************************************************************************/
/* BANK 1 - Individual Address Registers */

#define LAN91C111_IAR01                     (*(vuint16  *)(void *)(&__ETHERNET[0x04]))
#define LAN91C111_IAR23                     (*(vuint16  *)(void *)(&__ETHERNET[0x06]))
#define LAN91C111_IAR45                     (*(vuint16  *)(void *)(&__ETHERNET[0x08]))

/************************************************************************************************************/
/* BANK 1 - General Purpose Register */
#define LAN91C111_GP_REG        0x000A

/************************************************************************************************************/
/* BANK 1 - Control Register */
/*BigEndian OK */
#define LAN91C111_CTRLR                     (*(vuint16  *)(void *)(&__ETHERNET[0x0C]))

/* Control Register Bit Definitions */
#define LAN91C111_CTRLR_RCV_BAD             0x0040 // When 1 bad CRC packets are received
#define LAN91C111_CTRLR_AUTO_RELEASE        0x0008 // When 1 tx pages are released automatically
#define LAN91C111_CTRLR_LE_ENABLE           0x8000 // When 1 enables Link Error interrupt
#define LAN91C111_CTRLR_CR_ENABLE           0x4000 // When 1 enables Counter Rollover interrupt
#define LAN91C111_CTRLR_TE_ENABLE           0x2000 // When 1 enables Transmit Error interrupt
#define LAN91C111_CTRLR_EEPROM_SELECT       0x0400 // Controls EEPROM reload & store
#define LAN91C111_CTRLR_RELOAD              0x0200 // When set reads EEPROM into registers
#define LAN91C111_CTRLR_STORE               0x0100 // When set stores registers into EEPROM

/************************************************************************************************************/
/* BANK 2 - MMU Command Register */
/*BigEndian OK */
#define LAN91C111_MMCR                      (*(vuint16  *)(void *)(&__ETHERNET[0x00]))

/* MMU Command Register Bit Definitions */
#define LAN91C111_MMCR_BUSY                 0x0100  // When 1 the last release has not completed
#define LAN91C111_MMCR_NOP                  (0<<13) // No Op
#define LAN91C111_MMCR_ALLOC                (1<<13) // OR with number of 256 byte packets
#define LAN91C111_MMCR_RESET                (2<<13) // Reset MMU to initial state
#define LAN91C111_MMCR_REMOVE               (3<<13) // Remove the current rx packet
#define LAN91C111_MMCR_RELEASE              (4<<13) // Remove and release the current rx packet
#define LAN91C111_MMCR_FREEPKT              (5<<13) // Release packet in PNR register
#define LAN91C111_MMCR_ENQUEUE              (6<<13) // Enqueue the packet for transmit
#define LAN91C111_MMCR_RSTTXFIFO            (7<<13) // Reset the TX FIFOs

/************************************************************************************************************/
/* BANK 2 - Packet Number Register */
/*BigEndian OK */
#define LAN91C111_PNR                       (*(vuint16  *)(void *)(&__ETHERNET[0x02]))

/************************************************************************************************************/
/* BANK 2 - Allocation Result Register */
/*BigEndian OK */
#define LAN91C111_ARR                       (*(vuint16  *)(void *)(&__ETHERNET[0x03]))

/* Allocation Result Register Bit Definitions */
#define LAN91C111_ARR_FAILED                0x0080  // Alocation Failed

/************************************************************************************************************/
/* BANK 2 - RX FIFO Ports Register*/
/*BigEndian OK */
#define LAN91C111_RXFIFOR                   (*(vuint16  *)(void *)(&__ETHERNET[0x04]))

#define LAN91C111_RXFIFOR_REMPTY            0x0080  // RX FIFO Empty
#define LAN91C111_RXFIFOR_PKTMASK           0x003F  // RX pkt # mask 
/* rx packet # */
#define LAN91C111_RXFIFOR_PKT               (LAN91C111_RXFIFOR & LAN91C111_RXFIFOR_PKTMASK)

/************************************************************************************************************/
/* BANK 2 - TX FIFO Ports Register */
/*BigEndian OK */
#define LAN91C111_TXFIFOR                   LAN91C111_RXFIFOR   // Must be read as a word

#define LAN91C111_TXFIFOR_EMPTY             0x8000  // TX FIFO Empty
#define LAN91C111_TXFIFOR_PKTMASK           0x3F00  // TX pkt # mask
/* tx packet # */
#define LAN91C111_TXFIFOR_PKT               (LAN91C111_TXFIFOR & LAN91C111_TXFIFOR_PKTMASK >> 8);


/************************************************************************************************************/
/* BANK 2 - Pointer Register */
/* BigEndian OK */
#define LAN91C111_PTR                       (*(vuint16  *)(void *)(&__ETHERNET[0x06]))