sysinit.c

motorola 针对coldfire 5275 评估板的Dbug bootloader源程序

/*
 * File:        sysinit.c
 * Purpose:     Reset configuration of the M5275EVB
 *
 * Notes:       
 */

#include "src/include/dbug.h"
#include "src/cpu/coldfire/mcf5xxx/mcf5xxx_uart.h"

/********************************************************************/

void mcf5275_init(void);
void mcf5275_pll_init(void);
void mcf5275_scm_init(void);
void mcf5275_uart_init(void);
void mcf5275_cs_init(void);
void mcf5275_sdram_init(void);
void mcf5275_wtm_init(void);

/********************************************************************/
void
mcf5275_init(void)
{
    mcf5275_wtm_init();
    mcf5275_pll_init();
    mcf5275_cs_init();
    mcf5275_scm_init();
    mcf5275_sdram_init();
    mcf5275_uart_init();
}   
/********************************************************************/
void 
mcf5275_pll_init(void)
{
    /*
     * Multiply 25Mhz reference crystal to acheive system clock of 150Mhz
     */
    MCF_FMPLL_SYNCR = MCF_FMPLL_SYNCR_MFD(1) | MCF_FMPLL_SYNCR_RFD(0);

    /*
     * Wait for PLL to lock
     */     
    while (!(MCF_FMPLL_SYNSR & MCF_FMPLL_SYNSR_LOCK));
}
/****************************************************************/
void
mcf5275_scm_init(void)
{
    /* 
     * Enable on-chip modules to access internal SRAM 
     */
    MCF_SCM_RAMBAR = (0 
        | MCF_SCM_RAMBAR_BA(SRAM_ADDRESS>>16)
        | MCF_SCM_RAMBAR_BDE);
}
/********************************************************************/
void 
mcf5275_wtm_init(void)
{
    /*
     * Disable Software Watchdog Timer
     */
    MCF_WTM_WCR = 0;
}

/********************************************************************/
void
mcf5275_uart_init(void)
{
    /* 
     * Set Port UA to initialize URXD0/URXD1 UTXD0/UTXD1 
     */
    #if (DBUG_UART_PORT == 0)
        MCF_GPIO_PAR_UART = (0 |
            MCF_GPIO_PAR_UART_PAR_U0RTS | 
            MCF_GPIO_PAR_UART_PAR_U0CTS |
            MCF_GPIO_PAR_UART_PAR_U0TXD |
            MCF_GPIO_PAR_UART_PAR_U0RXD);
    #elif (DBUG_UART_PORT == 1)             
        MCF_GPIO_PAR_UART = (0 |
            MCF_GPIO_PAR_UART_PAR_U1RTS | 
            MCF_GPIO_PAR_UART_PAR_U1CTS |
            MCF_GPIO_PAR_UART_PAR_U1TXD |
            MCF_GPIO_PAR_UART_PAR_U1RXD);
    #elif (DBUG_UART_PORT == 2)
        MCF_GPIO_PAR_UART = (0 |
            MCF_GPIO_PAR_UART_PAR_U2TXD |
            MCF_GPIO_PAR_UART_PAR_U2RXD |
            MCF_GPIO_PAR_UART_PAR_U2CTS_UART2 |
            MCF_GPIO_PAR_UART_PAR_U2RTS_UART2);
    #else
    #error "Invalid DBUG_UART_PORT setting"
    #endif

    mcf5xxx_uart_init(DBUG_UART_PORT, SYSTEM_CLOCK, board_get_baud());
}
/********************************************************************/
void
mcf5275_sdram_init(void)
{
    /* Initialize DDR on the M5275EVB board */
    
    /* 
     * Initialize PAR to enable SDRAM signals 
     */ 
    MCF_GPIO_PAR_SDRAM = 0x03FF;

    /*
     * Check to see if the SDRAM has already been initialized
     * by a run control tool
     */
    if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
    {
        /* Initialize SDRAM chip select */
        MCF_SDRAMC_SDBAR0 = (0
            | MCF_SDRAMC_SDBARn_BASE(SDRAM_ADDRESS)
            );
            
        MCF_SDRAMC_SDMR0 = (0
            | MCF_SDRAMC_SDMRn_BAM_32M
            | MCF_SDRAMC_SDMRn_V
            );            

        /* Initialize timing parameters */
//      MCF_SDRAMC_SDCFG1 = (0
//          | MCF_SDRAMC_SDCFG1_SRD2RW(SDRAM_BL/2)
//          | MCF_SDRAMC_SDCFG1_SWT2RD((SDRAM_TWR/PERIOD) + 1)
//          | MCF_SDRAMC_SDCFG1_RDLAT(SDRAM_DBL_CASL + 2)
//          | MCF_SDRAMC_SDCFG1_ACT2RW((SDRAM_TRCD/PERIOD) - 1 + 1) /* 1 added to round up */
//          | MCF_SDRAMC_SDCFG1_PRE2ACT((SDRAM_TRP/PERIOD) - 1 + 1) /* 1 added to round up */
//          | MCF_SDRAMC_SDCFG1_REF2ACT((SDRAM_TRFC/PERIOD) - 1 + 1) /* 1 added to round up */
//          | MCF_SDRAMC_SDCFG1_WTLAT(3)   
//          );

//      MCF_SDRAMC_SDCFG2 = (0
//          | MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2)
//          | MCF_SDRAMC_SDCFG2_BWT2RW((SDRAM_BL/2) + (SDRAM_TWR/PERIOD))
//          | MCF_SDRAMC_SDCFG2_BRD2WT(SDRAM_BL)
//          | MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1)      
//          );

//      MCF_SDRAMC_SDCFG1 = 0x43711630;
//      MCF_SDRAMC_SDCFG2 = 0x46B70000;            

        MCF_SDRAMC_SDCFG1 = 0x83711630;
        MCF_SDRAMC_SDCFG2 = 0x46770000;     
            
        /* Enable clock and write to SDMR */
        MCF_SDRAMC_SDCR = (0
            | MCF_SDRAMC_SDCR_MODE_EN
            | MCF_SDRAMC_SDCR_CKE
            );
        
        /* Set IPALL bit */     
        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;                   
            
        /* Dummy write to SDRAM to issue PALL */
        *(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
        
        /* Write extended mode register */
        MCF_SDRAMC_SDMR = (0
            | MCF_SDRAMC_SDMR_BNKAD_LEMR
            | MCF_SDRAMC_SDMR_AD(0x0)
            | MCF_SDRAMC_SDMR_CMD        
            );
                    
        /* Dummy write to SDRAM to issue LEMR */
        *(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
        
        /* Write mode register and reset DLL 
        MCF_SDRAMC_SDMR = (0
            | MCF_SDRAMC_SDMR_BNKAD_LMR
            | MCF_SDRAMC_SDMR_AD(0x58D)
            | MCF_SDRAMC_SDMR_CMD        
            );  
          */      
       MCF_SDRAMC_SDMR = 0x058D0000;
                         
        /* Dummy write to SDRAM to issue LMR */
        *(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
        
        /* Clear SDMR CMD bit to stop issuing LMR/LEMR commands */
        MCF_SDRAMC_SDMR &= ~(MCF_SDRAMC_SDMR_CMD);    
        
        /* Execute a PALL command */
        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
                
        /* Dummy write to SDRAM to issue PALL */
        *(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
        
        /* Clear IPALL bit to stop issuing PALL commands */
        MCF_SDRAMC_SDCR &= ~(MCF_SDRAMC_SDCR_IPALL);
         
        /* Perform two REF cycles */
        MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
        
        /* Dummy write to SDRAM to issue first REF */
        *(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;

        /* Dummy write to SDRAM to issue second REF */
        *(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
        
        /* Write mode register and clear reset DLL 
        MCF_SDRAMC_SDMR = (0
            | MCF_SDRAMC_SDMR_BNKAD_LMR
            | MCF_SDRAMC_SDMR_AD(0x18D)
            | MCF_SDRAMC_SDMR_CMD        
            );
            */
        MCF_SDRAMC_SDMR = 0x018D0000;
                
        /* Dummy write to SDRAM to issue LMR */
        *(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;
        
        /* Clear SDMR CMD bit to stop issuing LMR/LEMR commands */
        MCF_SDRAMC_SDMR &= ~(MCF_SDRAMC_SDMR_CMD);
        
        MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;         
        
        /* Enable auto refresh and lock SDMR */
        MCF_SDRAMC_SDCR = (0
            | MCF_SDRAMC_SDCR_CKE
            | MCF_SDRAMC_SDCR_REF
            | MCF_SDRAMC_SDCR_MUX(1)
            | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(int)(SYSTEM_CLK_PERIOD*64)) - 1 + 1) /* 1 added to round up */
            | MCF_SDRAMC_SDCR_DQS_OE(0x3) 
            );
    }
}
/********************************************************************/
void
mcf5275_cs_init(void)
{
    /* 
     * ChipSelect 1 - External SRAM 
     */
    MCF_CS_CSAR1 = MCF_CS_CSAR_BA(EXT_SRAM_ADDRESS);
    MCF_CS_CSCR1 = (0
        | MCF_CS_CSCR_IWS(0)
        | MCF_CS_CSCR_AA
        | MCF_CS_CSCR_PS_32);
    MCF_CS_CSMR1 = MCF_CS_CSMR_BAM_512K | MCF_CS_CSMR_V;

    /* 
     * ChipSelect 0 - External Flash 
     */ 
    MCF_CS_CSAR0 = MCF_CS_CSAR_BA(FLASH_ADDRESS);
    MCF_CS_CSCR0 = (0
        | MCF_CS_CSCR_IWS((int)(AMD_FLASH_SPEED/SYSTEM_CLK_PERIOD))
        | MCF_CS_CSCR_AA
        | MCF_CS_CSCR_PS_16);
    MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V;
}
/********************************************************************/