📄 m5275evb.c
字号:
/*
* File: m5275evb.c
* Purpose: Board specific routines for the M5275EVB
*
* Notes:
*
*/
#include "src/include/dbug.h"
#include "src/dev/flash/amd_flash.h"
#ifdef DBUG_NETWORK
#include "src/uif/net/net.h"
#include "src/cpu/coldfire/mcf5xxx/mcf5xxx_timer.h"
#include "src/cpu/coldfire/mcf5xxx/mcf5xxx_fecx.h"
extern NIF nif1;
#endif
/********************************************************************/
/*
* Global BSP variables referenced by dBUG
*/
const char BRD_STR[] = "M5275EVB";
const int BRD_VER_MAJOR = 1;
const char BRD_VER_MINOR = 'b';
const char COPYRIGHT2[] = "";
/********************************************************************/
void
board_init (void)
{
extern REGISTERS context;
/*
* Point VBR to the vector table which is copied to RAM in main()
*/
mcf5xxx_wr_vbr((uint32)__VECTOR_RAM);
/*
* Determine cause(s) of Reset
*/
printf("\n\n");
if (MCF_SCM_CRSR & MCF_SCM_CRSR_CWDR)
printf("Core Watchdog Time Reset\n");
if (MCF_RCM_RSR & MCF_RCM_RSR_EXT)
printf("External Reset\n");
if (MCF_RCM_RSR & MCF_RCM_RSR_LOC)
printf("Loss of Clock Reset\n");
if (MCF_RCM_RSR & MCF_RCM_RSR_LOL)
printf("Loss of PLL Lock Reset\n");
if (MCF_RCM_RSR & MCF_RCM_RSR_SOFT)
printf("Software Reset\n");
if (MCF_RCM_RSR & MCF_RCM_RSR_WDR)
printf("Watchdog Timer Reset\n");
if (MCF_RCM_RSR & MCF_RCM_RSR_POR)
printf("Power-on Reset\n");
/*
* Allow interrupts from IRQ7 (black button)
*/
MCF_GPIO_PAR_IRQ |= MCF_GPIO_PAR_IRQ_PAR_IRQ7;
MCF_EPORT_EPIER = MCF_EPORT_EPIER_EPIE7;
MCF_INTC0_IMRL &= ~(MCF_INTC0_INTFRCL_INT7 | MCF_INTC0_IMRL_MASKALL);
/*
* Set dBUG user stack to top of SDRAM (master mode)
*/
context.a7 = (SDRAM_ADDRESS + SDRAM_SIZE);
}
/********************************************************************/
void
board_init2 (void)
{
/*
* The Timer routines cannot be called until after isr_init()
* Check main() for calling order of xxxx_init() functions.
*/
/* Initialize the Network Timer */
#if (defined(DBUG_NETWORK))
timer_init(TIMER_NETWORK, TIMER_NETWORK_PERIOD,
SYSTEM_CLOCK, TIMER_NETWORK_LEVEL, NULL);
#endif
}
/*******************************************************************/
void
board_init3 (void)
{
FLASH_INFO Am29LV160CB;
strcpy(Am29LV160CB.name,"Am29LV160CB (1 x 16-bit)");
Am29LV160CB.base = (ADDRESS) AMD_FLASH_ADDRESS;
Am29LV160CB.mask = AMD_FLASH_CELL_MASK;
Am29LV160CB.size = (int) AMD_FLASH_SIZE;
Am29LV160CB.erase = (void *) amd_flash_erase;
Am29LV160CB.program = (void *) amd_flash_program;
Am29LV160CB.sector_start = (void *) amd_flash_sector_start;
Am29LV160CB.sector_end = (void *) amd_flash_sector_end;
Am29LV160CB.putchar = (void *) board_putchar;
Am29LV160CB.protect_start = (ADDRESS) DBUG_ADDRESS;
Am29LV160CB.protect_size = (int) DBUG_SIZE;
/*
* Initialize AMD Flash device
*/
amd_flash_init(Am29LV160CB.base);
/*
* Register AMD Flash with dBUG Flash Utilities
*/
flash_register_device(&Am29LV160CB);
}
/********************************************************************/
int
board_dlio_init (void)
{
/*
* Download initialization routine
*/
#ifdef DBUG_NETWORK
int vector;
int (*handler)(void *, void *);
uint8* board_get_ethaddr(uint8*);
if (uif_dlio == UIF_DLIO_NETWORK)
{
unsigned char mac[6];
/*
* Register all FEC interrupt vectors with handler
* The FEC interrupt vectors are assigned to sources
* 23 to 35 on INTC0
*/
/*
* Register the FEC0 interrupt handler
*/
handler = fec_irq_handler;
#if (DBUG_ETHERNET_PORT ==0)
{
for (vector = (64 + 23); vector <= (64 + 35); vector++)
{
if (!isr_register_handler(ISR_DBUG_ISR,
vector,
handler,
(void *)&nif1,
NULL))
{
#ifdef DEBUG_PRINT
printf("Error: Unable to register handler\n");
#endif
return FALSE;
}
}
}
#else
{
for (vector = (128 + 23); vector <= (128 + 35); vector++)
{
if (!isr_register_handler(ISR_DBUG_ISR,
vector,
handler,
(void *)&nif1,
NULL))
{
#ifdef DEBUG_PRINT
printf("Error: Unable to register handler\n");
#endif
return FALSE;
}
}
}
#endif
/*
* Enable FEC interrupts to the ColdFire core
* Setup each ICR with a unique interrupt level/priority combination
*/
#if (DBUG_ETHERNET_PORT == 0)
{
/* FEC Rx Frame */
MCF_INTC0_ICRn(27) = MCF_INTC0_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC0_ICRn_IP(7);
/* FEC Rx Buffer */
MCF_INTC0_ICRn(28) = MCF_INTC0_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC0_ICRn_IP(6);
/* FEC Tx Frame */
MCF_INTC0_ICRn(23) = MCF_INTC0_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC0_ICRn_IP(5);
/* FEC Tx Buffer */
MCF_INTC0_ICRn(24) = MCF_INTC0_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC0_ICRn_IP(4);
/* FEC FIFO Underrun */
MCF_INTC0_ICRn(25) = MCF_INTC0_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC0_ICRn_IP(3);
/* FEC Collision Retry Limit */
MCF_INTC0_ICRn(26) = MCF_INTC0_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC0_ICRn_IP(2);
/* FEC MII */
MCF_INTC0_ICRn(29) = MCF_INTC0_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC0_ICRn_IP(1);
/* FEC Late Collision */
MCF_INTC0_ICRn(30) = MCF_INTC0_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC0_ICRn_IP(0);
/* FEC Heartbeat Error */
MCF_INTC0_ICRn(31) = MCF_INTC0_ICRn_IL(FEC_LEVEL_LOW) |
MCF_INTC0_ICRn_IP(7);
/* FEC Graceful Stop Comlete */
MCF_INTC0_ICRn(32) = MCF_INTC0_ICRn_IL(FEC_LEVEL_LOW) |
MCF_INTC0_ICRn_IP(6);
/* FEC Bus Error */
MCF_INTC0_ICRn(33) = MCF_INTC0_ICRn_IL(FEC_LEVEL_LOW) |
MCF_INTC0_ICRn_IP(5);
/* FEC Babbling Transmit */
MCF_INTC0_ICRn(34) = MCF_INTC0_ICRn_IL(FEC_LEVEL_LOW) |
MCF_INTC0_ICRn_IP(4);
/* FEC Babbling Receive */
MCF_INTC0_ICRn(35) = MCF_INTC0_ICRn_IL(FEC_LEVEL_LOW) |
MCF_INTC0_ICRn_IP(3);
/* Enable the FEC interrupts in the mask register */
MCF_INTC0_IMRL &= ~(MCF_INTC0_IMRL_INT_MASK23 |
MCF_INTC0_IMRL_INT_MASK24 |
MCF_INTC0_IMRL_INT_MASK25 |
MCF_INTC0_IMRL_INT_MASK26 |
MCF_INTC0_IMRL_INT_MASK27 |
MCF_INTC0_IMRL_INT_MASK28 |
MCF_INTC0_IMRL_INT_MASK29 |
MCF_INTC0_IMRL_INT_MASK30 |
MCF_INTC0_IMRL_INT_MASK31 |
MCF_INTC0_IMRL_MASKALL);
MCF_INTC0_IMRH &= ~(MCF_INTC0_IMRH_INT_MASK32 |
MCF_INTC0_IMRH_INT_MASK33 |
MCF_INTC0_IMRH_INT_MASK34 |
MCF_INTC0_IMRH_INT_MASK35);
/* Initialize PAR to enable Ethernet signals */
MCF_GPIO_PAR_FECI2C |= (0 |
MCF_GPIO_PAR_FECI2C_PAR_MDIO0_FEC |
MCF_GPIO_PAR_FECI2C_PAR_MDC0_FEC);
MCF_GPIO_PAR_FEC0HL = (0 |
MCF_GPIO_PAR_FEC0HL_PAR_FEC0L |
MCF_GPIO_PAR_FEC0HL_PAR_FEC0H);
}
#else
{
/* FEC Rx Frame */
MCF_INTC1_ICRn(27) = MCF_INTC1_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC1_ICRn_IP(7);
/* FEC Rx Buffer */
MCF_INTC1_ICRn(28) = MCF_INTC1_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC1_ICRn_IP(6);
/* FEC Tx Frame */
MCF_INTC1_ICRn(23) = MCF_INTC1_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC1_ICRn_IP(5);
/* FEC Tx Buffer */
MCF_INTC1_ICRn(24) = MCF_INTC1_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC1_ICRn_IP(4);
/* FEC FIFO Underrun */
MCF_INTC1_ICRn(25) = MCF_INTC1_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC1_ICRn_IP(3);
/* FEC Collision Retry Limit */
MCF_INTC1_ICRn(26) = MCF_INTC1_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC1_ICRn_IP(2);
/* FEC MII */
MCF_INTC1_ICRn(29) = MCF_INTC1_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC1_ICRn_IP(1);
/* FEC Late Collision */
MCF_INTC1_ICRn(30) = MCF_INTC1_ICRn_IL(FEC_LEVEL_HIGH) |
MCF_INTC1_ICRn_IP(0);
/* FEC Heartbeat Error */
MCF_INTC1_ICRn(31) = MCF_INTC1_ICRn_IL(FEC_LEVEL_LOW) |
MCF_INTC1_ICRn_IP(7);
/* FEC Graceful Stop Comlete */
MCF_INTC1_ICRn(32) = MCF_INTC1_ICRn_IL(FEC_LEVEL_LOW) |
MCF_INTC1_ICRn_IP(6);
/* FEC Bus Error */
MCF_INTC1_ICRn(33) = MCF_INTC1_ICRn_IL(FEC_LEVEL_LOW) |
MCF_INTC1_ICRn_IP(5);
/* FEC Babbling Transmit */
MCF_INTC1_ICRn(34) = MCF_INTC1_ICRn_IL(FEC_LEVEL_LOW) |
MCF_INTC1_ICRn_IP(4);
/* FEC Babbling Receive */
MCF_INTC1_ICRn(35) = MCF_INTC1_ICRn_IL(FEC_LEVEL_LOW) |
MCF_INTC1_ICRn_IP(3);
/* Enable the FEC interrupts in the mask register */
MCF_INTC1_IMRL &= ~(MCF_INTC1_IMRL_INT_MASK23 |
MCF_INTC1_IMRL_INT_MASK24 |
MCF_INTC1_IMRL_INT_MASK25 |
MCF_INTC1_IMRL_INT_MASK26 |
MCF_INTC1_IMRL_INT_MASK27 |
MCF_INTC1_IMRL_INT_MASK28 |
MCF_INTC1_IMRL_INT_MASK29 |
MCF_INTC1_IMRL_INT_MASK30 |
MCF_INTC1_IMRL_INT_MASK31 |
MCF_INTC1_IMRL_MASKALL);
MCF_INTC1_IMRH &= ~(MCF_INTC1_IMRH_INT_MASK32 |
MCF_INTC1_IMRH_INT_MASK33 |
MCF_INTC1_IMRH_INT_MASK34 |
MCF_INTC1_IMRH_INT_MASK35);
/* Initialize PAR to enable Ethernet signals */
MCF_GPIO_PAR_FECI2C |= (0 |
MCF_GPIO_PAR_FECI2C_PAR_MDIO1 |
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -