m5275evb.cfg

motorola 针对coldfire 5275 评估板的Dbug bootloader源程序

ResetHalt
Delay 200
Stop

; Set VBR to the beginning of what will be SDRAM
; VBR is an absolute CPU register
; SDRAM is at 0x00000000+0x0400000
writecontrolreg 0x0801 0x10000000

; Set RAMBAR = 0x20000001
; RAMBAR is an absolute CPU register
; This is the location of the internal 64k of SRAM on the chip
writecontrolreg 0x0C05 0x20000001

; set SYNCR to 150MHz
writemem.l 0x40120000 0x01000000
delay 1000


; Set PAR_SDRAM to allow SDRAM signals to be enabled
writemem.w 0x40100080 0x03FF

; Turn off WCR
writemem.b 0x40140000  0x0000

; 1MB ASRAM on CS1 at 0x30000000

writemem.w 0x4000008C   0x3000		; CSAR1
writemem.l 0x40000090   0x000F0001	; CSMR1
writemem.w 0x40000096   0x3D20		; CSCR1

; 2MB FLASH on CS0 at 0xFFE00000

writemem.w 0x40000080   0xFFE0		; CSAR0
writemem.l 0x40000084   0x001F0001	; CSMR0
writemem.w 0x4000008A   0x1980		; CSCR0


delay 100
; Set up CS0 address space
writemem.l 0x40000050   0x00000000  ; SDBAR0 
writemem.l 0x40000054   0x00FC0001  ; SDMR0 
writemem.l 0x40000048   0x83711630  ; SDCFG1
writemem.l 0x4000004C   0x46B70000  ; SDCFG2

; Set INIT_MD and CKE bits
writemem.l 0x40000044   0xC0000000  ; SDCR


; Set SW_PRE bit and issue PALL command
writemem.l 0x40000044   0xC0000002  ; SDCR
writemem.l 0x00000000   0x12345678  ; SDRAM

; Set SW_MOD bit and issue EMRS command
writemem.l 0x40000040   0x40010000  ; SDMR
writemem.l 0x00000000   0x12345678  ; SDRAM

; Issue MRS command
writemem.l 0x40000040   0x058D0000  ; SDMR
writemem.l 0x00000000   0x12345678  ; SDRAM

; wait for DLL
delay 1000

; Clear SW_MOD bit
writemem.l 0x40000040   0x058C0000  ; SDMR

; Set SW_PRE bit and issue PALL command
writemem.l 0x40000044   0xC0000002  ; SDCR
writemem.l 0x00000000   0x12345678  ; SDRAM

; Clear SW_PRE bit
writemem.l 0x40000044   0xC0000000  ; SDCR

; Set SW_REF bit and issue 2 AREF commands
writemem.l 0x40000044   0xC0000004  ; SDCR
writemem.l 0x00000000   0x12345678  ; SDRAM
writemem.l 0x00000000   0x12345678  ; SDRAM

; Set SW_MOD bit and issue MRS command
writemem.l 0x40000040   0x018D0000  ; SDMR
writemem.l 0x00000000   0x12345678  ; SDRAM

; Clear SW_MOD bit
writemem.l 0x40000040   0x018C0000  ; SDMR

; Clear INIT_MD bit 
writemem.l 0x40000044   0x40000004  ; SDCR

; Write to control register (clear MODE_EN)
writemem.l 0x40000044   0x51090C00  ; SDCR

; Wait a bit
delay 100