📄 init.s.bak
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;
;/* Define extern function references. */
;
;VOID init_crc32(VOID);
;ULONG crc32(UCHAR *buf,INT len);
;ULONG test_ram(ULONG addr,ULONG len);
XREF _init_crc32
XREF _crc32
XREF STKTOP
XREF _main
SECTION .bss
;-------------------------------------------------------------
;Test Product Output Flag
;ULONG _Test_Product_Flag
XDEF _Test_Product_Flag
_Test_Product_Flag:
DS.B 4
;-------------------------------------------------------------
MBAR_ADDR EQU $30000000 ; Base address of all internal regs
CTRL_CODE_ADDR EQU $101E0000 ; CTRL Address in Flash , for 2MB flash ,2002.4.24
CTRL_CODE_ADDR1 EQU $002e0000 ; CTRL Address in,DRAM for VIA,2002.4.24,wuyujun
CTRL_CODE_ADDR2 EQU $002e0434 ; CTRL CODE begin Address in DRAM
CTRL_CODE_LEN EQU $1fff0 ; CTRL Length 128K
CTRL_CODE_CRC EQU $101FFFF0 ; CTRL Code CRC address
;MAIN_CODE_ADDR EQU $00350000 ; MAIN Address in DRAM
FLASH_BASE_ADDR EQU $10000000 ; Base address of flash
;FLASH_LENGTH EQU $100000
FLASH_LENGTH EQU $200000 ; flash length 2MB for using in vt6526, wuyujun
CACR EQU $002 ; Cache Control Register
CACHE_INV EQU $01000000 ; Value to invalidate entire cache
CACHE_EN EQU $80000000 ; Value to enable the cache
ISRAM_ADDR EQU $40000000 ; isram base address
ISRAM_CODE_LEN EQU $1800 ; 6K
ISRAM_LEN EQU $2000 ; 8K
;AL300_ADDRESS EQU $50000000 ; AL300A registers base addr
;MAC_ADDRESS_ADDR EQU $10003FF0 ; MAC_ADDRESS
TMR1 EQU $100 ; Offset of Timer 1 Mode Register
TRR1 EQU $104 ; Offset of Timer 1 Reference Reg
TER1 EQU $111 ; Offset of Timer 1 Event Register
ICR9 EQU $1c ; Offset of Timer 1 Int Control Reg
TCN1 EQU $10c ; tcn1
TMR1_CFG EQU $0d ; Value to configure Timer 1
;1d - enable interrupt , 0d - disable interrupt.
TRR1_LOAD EQU $ffff ; Value to be compared to counter
TER1_CLEAR EQU $ff ; Value to clear timer interrupt
ICR9_CFG EQU $8f ; timer 1 int : level 3, pri 3
TIMER1_10MS_COUNT EQU $61a8 ; 10ms
;
SECTION .sdata2
ALIGN 2
XDEF _INT_Vectors
_INT_Vectors:
DC.L STKTOP-4 ; Initial stack value 0
DC.L start ; System entry location 1
XDEF _INT_Version
_INT_Version:
ASCII "STAR-SWITCH-BOOT"
ASCII "01-01-01 "
ASCII "2002-06-28 \0"
DC.L 0
SECTION .text
XDEF _INT_Initialize
XDEF start
_INT_Initialize:
start:
;VOID INT_Initialize(void)
;{
; // Initialize temporary stack pointer
MOVE.L #___SP_INIT,A7
; // Initialize a5 to sdata (provided by linker)
; MOVE.L #__SDA_BASE_,A5 ; ---> no need
;
; // Lockout interrupts during initialization.
MOVE.W #$2700,SR
; --> VBR的初始化
MOVE.L A7,D1
MOVE.L #0,D0
MOVEA.L D0,A7
MOVEC.L A7,VBR
MOVEA.L D1,A7
; // init neccesary register: MBAR, RAMBAR, CS0, DRAM
MOVE.L #$30000001,D0 ; NOT using MBAR_ADDR
MOVEC.L D0,MBAR
MOVE.L #$40000001,D0
MOVEC.L D0,RAMBAR
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ICR
MOVE.L #0x0,D0 ;0x0
MOVE.B D0,(MBAR_ADDR+$3) ;SIMR
MOVE.L #0x85,D0 ;
MOVE.B D0,(MBAR_ADDR+$14) ;
MOVE.L #0x8B,D0 ;
MOVE.B D0,(MBAR_ADDR+$15) ;
MOVE.L #0x8E,D0 ;
MOVE.B D0,(MBAR_ADDR+$16) ;
MOVE.L #0x92,D0 ;
MOVE.B D0,(MBAR_ADDR+$17) ;
MOVE.L #0x95,D0 ;
MOVE.B D0,(MBAR_ADDR+$18) ;
MOVE.L #0x98,D0 ;
MOVE.B D0,(MBAR_ADDR+$19) ;
MOVE.L #0x9F,D0 ;
MOVE.B D0,(MBAR_ADDR+$1A) ;
MOVE.L #0x1E,D0 ;
MOVE.B D0,(MBAR_ADDR+$1B) ;
MOVE.L #0x97,D0 ;
MOVE.B D0,(MBAR_ADDR+$1C) ;
MOVE.L #0x96,D0 ;
MOVE.B D0,(MBAR_ADDR+$1D) ;
MOVE.L #0x8C,D0 ;
MOVE.B D0,(MBAR_ADDR+$1E) ;
MOVE.L #0x8E,D0 ;
MOVE.B D0,(MBAR_ADDR+$1F) ;
MOVE.L #0x8D,D0 ;
MOVE.B D0,(MBAR_ADDR+$20) ;
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+0x36) ;IMR
;;; MOVE.W #0x300,D0 ; SET PARALLEL PORT, NOT BDM DEBUG MODE
;;; MOVE.W D0,(MBAR_ADDR+0xCA) ;PAR
MOVE.L #$0,D0 ;SET ALL TO ZERO
MOVE.B D0,(MBAR_ADDR+$1C9) ;PPDAT =1
MOVE.L #$ff,D0 ;SET DIRECT TO OUTPUT
MOVE.B D0,(MBAR_ADDR+$1C5) ;PADDR
; // Initialize chip select registers
MOVE.L #$1000,D0 ; CS0
MOVE.W D0,(MBAR_ADDR+$64) ; CSAR0
MOVE.L #$1F0000,D0
MOVE.L D0,(MBAR_ADDR+$68) ; CSMR0 flash size = 0x100000
;MOVE.L #$3D83,D0 ; WS = 15?
MOVE.L #$1593,D0 ; WS = 5,5*25ns=125ns,ASET=1,Address Setup 1 Clock
MOVE.W D0,(MBAR_ADDR+$6E) ; CSCR0
MOVE.L #$3DC0,D0
MOVE.W D0,(MBAR_ADDR+$7A) ;cs1 disable
MOVE.L #0x5000,D0 ;CS2
MOVE.W D0,(MBAR_ADDR+0x7c) ;CSAR2
MOVE.L #0x0,D0
MOVE.L D0,(MBAR_ADDR+0x80) ;CSMR2
MOVE.L #0x118f,D0
MOVE.W D0,(MBAR_ADDR+0x86) ;CSCR2
;MOVE.L #0x5000,D0 ;CS3 --> AL300A
;MOVE.W D0,(MBAR_ADDR+0x88) ;CSAR3
;MOVE.L #0x0,D0
;MOVE.L D0,(MBAR_ADDR+0x8C) ;CSMR3
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+0x92) ;CSCR3
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; MOVE.L #AL300_ADDRESS,A0
; MOVE.L #0,(A0) ;D0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+0x9E) ;CSCR4
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+0xAA) ;CSCR5
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+0xB6) ;CSCR6
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+0xC2) ;CSCR7
MOVE.L #0x0300,D0
MOVE.W D0,(MBAR_ADDR+0xC6) ;DMCR
; // init DRAM controller
;MOVE.L #$0,D0
MOVE.L #$27,D0
MOVE.W D0,(MBAR_ADDR+$46) ; DCRR
MOVE.L #$D020,D0
MOVE.W D0,(MBAR_ADDR+$4A) ; DCTR
MOVE.L #$0,D0
MOVE.W D0,(MBAR_ADDR+$4C) ; DCAR0
MOVE.L #$FE0000,D0
MOVE.L D0,(MBAR_ADDR+$50) ; DCMR0 DRAM size = 0x400000
MOVE.L #$27,D0
MOVE.B D0,(MBAR_ADDR+$57) ; DCCR0
; Cache
MOVE.L #CACHE_INV,D1 ; pick up Invalidate All command
MOVEC D1,CACR ; invalidate all cache lines
MOVE.L #CACHE_EN,D1 ; pick up Enable command
MOVEC D1,CACR ; enable the cache
; /* Set up Timer 1 for a 10ms periodic tick */
;
MOVE.L #ICR9_CFG,D0 ; Pick up configuration value for ICR9
MOVE.B D0,(MBAR_ADDR+ICR9) ; Setup Timer 1 interrupt for lev 3, pri 3
MOVE.L #TRR1_LOAD,D0 ; Pick up compare value
MOVE.W D0,(MBAR_ADDR+TRR1) ; Load into TRR1, val = (40MHz / 16) / 100
MOVE.L #TMR1_CFG,D0 ; Pick up configuration value for TMR1
MOVE.W D0,(MBAR_ADDR+TMR1) ; Setup Timer 1
; Prescaler = 0
; Disable reference interrupt
; Restart timer after reference reached
; System clock / 16
; Enable timer
; // Init UART
JSR _Init_UART
MOVE.L #12000000,D0 ;delay 600ms
jbsr _DELAY
MOVE.L #$1,D0 ;SET ALL TO ZERO
MOVE.B D0,(MBAR_ADDR+$1C9) ;PPDAT =1
JSR _Init_UART
MOVE.L #1200000,D0 ;delay 60ms
jbsr _DELAY
MOVE.L #$9,D0 ;SET ALL TO ZERO
MOVE.B D0,(MBAR_ADDR+$1C9) ;PPDAT =1
;delay 1s
MOVEQ.L #0,D1
MOVE.L D1,_Test_Product_Flag
MOVEQ.L #0,D7
;JSR _UART_Get_Char2 ;delay 1s
;CMP.L #'t',D1
;BNE .L2
;MOVEQ.L #1,D0
;MOVE.L D0,_Test_Product_Flag
;MOVE.L _Test_Product_Flag,D7
.L2:
TST.L D7
BEQ .L3
; // Send BOOT Version Message
MOVE.L #_BOOT_Version_Msg,A0
;Not in debug,don't send msg,2001/4/22,comment
JSR _BOOT_Send_Msg
.L3:
; // DRAM test
JSR _test_dram ; call test_dram()
CMP.L #0, D0 ; 0 ---> success
BNE _DRAM_Error
TST.L D7
BEQ .L4
MOVE.L #_Test_Dram_Passed_Msg,A0
JSR _BOOT_Send_Msg
.L4:
; // ISRAM test
JSR _test_isram ; call test_isram()
CMP.L #0, D0 ; 0 ---> success
BNE _ISRAM_Error
TST.L D7
BEQ .L5
MOVE.L #_Test_Isram_Passed_Msg,A0
JSR _BOOT_Send_Msg
.L5:
; // Init crc32_table
JSR _init_crc32
; // Check Ctrl CRC
MOVE.L #CTRL_CODE_ADDR,A0 ; A0 = CTRL ADDRESS in flash
MOVE.L (A0)+,D1 ; CRC
MOVE.L (4,A0),D0 ; TSIZE
ADDI.L #28,D0
CMP.L #CTRL_CODE_LEN,D0
JGT _CTRL_Error
MOVE.L D0, -(A7)
MOVE.L A0, -(A7)
JSR _crc32
ADDQ.L #8,A7
MOVE.L #CTRL_CODE_ADDR,A0 ;CRC stored in
MOVE.L (A0),D1
CMP.L D0,D1
BNE _CTRL_Error
TST.L D7
BEQ .L6
MOVE.L #_Check_Ctrl_Passed_Msg,A0
JSR _BOOT_Send_Msg
; // copy CTRL rom code to DRAM addr: 0x340000
MOVE.L #_Load_Ctrl_Msg,A0
JSR _BOOT_Send_Msg
.L6:
MOVE.L #CTRL_CODE_ADDR+4,A0
MOVE.L (A0)+,A2 ;TEXT IN RAM
MOVE.L (A0),D5 ;TSIZE
MOVE.L #CTRL_CODE_ADDR+$20, A1 ; CTRL code range: 0x100E0000-0x100fffff0
_Copy_Code:
;MOVEM.L (A1),D0-D3
MOVE.L (A1)+, D0
MOVE.L (A1)+, D1
MOVE.L (A1)+, D2
MOVE.L (A1)+, D3
MOVEM.L D0-D3,(A2)
MOVEM.L (A2),D0-D3
SUB.L #16,A1
MOVE.L (A1)+, D4
CMP.L D4,D0
BNE _LOAD_CTRL_Error
MOVE.L (A1)+, D4
CMP.L D4,D1
BNE _LOAD_CTRL_Error
MOVE.L (A1)+, D4
CMP.L D4,D2
BNE _LOAD_CTRL_Error
MOVE.L (A1)+, D4
CMP.L D4,D3
BNE _LOAD_CTRL_Error
ADD.L #16,A2
SUB.L #16, D5 ; LINE (CTRL code length)
CMP.L #0,D5
BGT _Copy_Code
;BNE _Copy_Code
TST.L D7
BEQ .L7
MOVE.L #_Load_Ctrl_Passed_Msg,A0
JSR _BOOT_Send_Msg
MOVE.L #_BOOT_Passed_Msg,A0
JSR _BOOT_Send_Msg
.L7:
_Jmp_To_DRAM:
; // jmp to DRAM
MOVE.W #$2700,SR ;close all interrupt
MOVE.L #CTRL_CODE_ADDR2, A0 ; --> CTRL program 从 0x340434 开始执行
JMP (A0)
; error, such as DRAM_error/ CRC_error
_CTRL_Error:
; // COPY MAIN CODE TO DRAM
MOVE.L #_Check_Ctrl_Failed_Msg,A0
JSR _BOOT_Send_Msg
MOVE.L #___RTEXT_ROM,A1
;MOVE.L #___RTEXT_ROM,D0
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