📄 urt_defs.h
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/*************************************************************************/
/* */
/* Copyright (c) 1999 Accelerated Technology, Inc. */
/* */
/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the */
/* subject matter of this material. All manufacturing, reproduction, */
/* use, and sales rights pertaining to this subject matter are governed */
/* by the license agreement. The recipient of this software implicitly */
/* accepts the terms of the license. */
/* */
/*************************************************************************/
/*************************************************************************/
/* */
/* FILE NAME VERSION */
/* */
/* urt_defs.h MCF5206/D 1.0 */
/* */
/* COMPONENT */
/* */
/* UART */
/* */
/* DESCRIPTION */
/* */
/* This file contains constant definitions and function macros */
/* for the UART module. */
/* */
/* AUTHOR */
/* */
/* Barry Sellew, Accelerated Technology, Inc. */
/* */
/* DATA STRUCTURES */
/* */
/* none */
/* */
/* DEPENDENCIES */
/* */
/* none */
/* */
/* HISTORY */
/* */
/* NAME DATE REMARKS */
/* */
/* Barry Sellew 04-16-1998 Created version 1.0 */
/* */
/*************************************************************************/
#ifndef URT_DEFS
#define URT_DEFS
/* The default system clock on the Coldire 5206 Arnwesh board is 50MHz */
#define SYSTEM_CLOCK 40000000//50000000
/* The MBAR register serves as the base address of the UART
control registers. */
#define MBAR 0x30000000
#define VBR 0x0
/* Macros for reading and writing the SIM interrupt control registers */
#define SET_ICR12_1(x) (*((CHAR *)(MBAR + 0x01F)) = x)
#define SET_ICR13_1(x) (*((CHAR *)(MBAR + 0x020)) = x)
#define SET_IMR_1(x) (*((USHORT *)(MBAR + 0x036)) = x)
#define READ_IMR_1() (*((USHORT *)(MBAR + 0x036)))
/* Defines for fields and bits of interrupt control registers */
#define ICR12_INT_LEVEL_1 0x0E
#define ICR13_INT_LEVEL_1 0x0D
#define IMR_UART1_MSK 0xEFFF
#define IMR_UART2_MSK 0xDFFF
#define IMR_UART1 0x1000
#define IMR_UART2 0x2000
/* Macros for reading and writing the UART1 control registers */
#define SET_UMR1_1(x) (*((CHAR *)(MBAR + 0x140)) = x)
#define SET_UMR2_1(x) (*((CHAR *)(MBAR + 0x140)) = x)
#define SET_UCSR_1(x) (*((CHAR *)(MBAR + 0x144)) = x)
#define SET_UCR_1(x) (*((CHAR *)(MBAR + 0x148)) = x)
#define SET_UTB_1(x) (*((CHAR *)(MBAR + 0x14C)) = x)
#define SET_UACR_1(x) (*((CHAR *)(MBAR + 0x150)) = x)
#define SET_UIMR_1(x) (*((CHAR *)(MBAR + 0x154)) = x)
#define SET_UBG1_1(x) (*((CHAR *)(MBAR + 0x158)) = x)
#define SET_UBG2_1(x) (*((CHAR *)(MBAR + 0x15C)) = x)
#define SET_UIVR_1(x) (*((CHAR *)(MBAR + 0x170)) = x)
#define READ_UMR1_1() (*((CHAR *)(MBAR + 0x140)))
#define READ_UMR2_1() (*((CHAR *)(MBAR + 0x140)))
#define READ_USR_1() (*((CHAR *)(MBAR + 0x144)))
#define READ_URB_1() (*((CHAR *)(MBAR + 0x14C)))
#define READ_UIPCR_1() (*((CHAR *)(MBAR + 0x150)))
#define READ_UISR_1() (*((CHAR *)(MBAR + 0x154)))
#define READ_UIVR_1() (*((CHAR *)(MBAR + 0x170)))
#define READ_UIP_1() (*((CHAR *)(MBAR + 0x174)))
/* Macros for reading and writing the UART2 control registers */
#define SET2_UMR1_1(x) (*((CHAR *)(MBAR + 0x180)) = x)
#define SET2_UMR2_1(x) (*((CHAR *)(MBAR + 0x180)) = x)
#define SET2_UCSR_1(x) (*((CHAR *)(MBAR + 0x184)) = x)
#define SET2_UCR_1(x) (*((CHAR *)(MBAR + 0x188)) = x)
#define SET2_UTB_1(x) (*((CHAR *)(MBAR + 0x18C)) = x)
#define SET2_UACR_1(x) (*((CHAR *)(MBAR + 0x190)) = x)
#define SET2_UIMR_1(x) (*((CHAR *)(MBAR + 0x194)) = x)
#define SET2_UBG1_1(x) (*((CHAR *)(MBAR + 0x198)) = x)
#define SET2_UBG2_1(x) (*((CHAR *)(MBAR + 0x19C)) = x)
#define SET2_UIVR_1(x) (*((CHAR *)(MBAR + 0x1B0)) = x)
#define READ2_UMR1_1() (*((CHAR *)(MBAR + 0x180)))
#define READ2_UMR2_1() (*((CHAR *)(MBAR + 0x180)))
#define READ2_USR_1() (*((CHAR *)(MBAR + 0x184)))
#define READ2_URB_1() (*((CHAR *)(MBAR + 0x18C)))
#define READ2_UIPCR_1() (*((CHAR *)(MBAR + 0x190)))
#define READ2_UISR_1() (*((CHAR *)(MBAR + 0x194)))
#define READ2_UIVR_1() (*((CHAR *)(MBAR + 0x1B0)))
#define READ2_UIP_1() (*((CHAR *)(MBAR + 0x1B4)))
/*define 5307 begin*/
/* Macros for reading and writing the SIM interrupt control registers */
#define SET_ICR4_2(x) (*((CHAR *)(MBAR + 0x050)) = x)
#define SET_ICR5_2(x) (*((CHAR *)(MBAR + 0x051)) = x)
#define SET_IMR_2(x) (*((ULONG *)(MBAR + 0x044)) = x)
#define READ_IMR_2() (*((ULONG *)(MBAR + 0x044)))
/* Defines for fields and bits of interrupt control registers */
#define ICR4_INT_LEVEL_2 0x0E
#define ICR5_INT_LEVEL_2 0x0D
/* Macros for reading and writing the UART1 control registers */
#define SET_UMR1_2(x) (*((CHAR *)(MBAR + 0x1C0)) = x)
#define SET_UMR2_2(x) (*((CHAR *)(MBAR + 0x1C0)) = x)
#define SET_UCSR_2(x) (*((CHAR *)(MBAR + 0x1C4)) = x)
#define SET_UCR_2(x) (*((CHAR *)(MBAR + 0x1C8)) = x)
#define SET_UTB_2(x) (*((CHAR *)(MBAR + 0x1CC)) = x)
#define SET_UACR_2(x) (*((CHAR *)(MBAR + 0x1D0)) = x)
#define SET_UIMR_2(x) (*((CHAR *)(MBAR + 0x1D4)) = x)
#define SET_UBG1_2(x) (*((CHAR *)(MBAR + 0x1D8)) = x)
#define SET_UBG2_2(x) (*((CHAR *)(MBAR + 0x1DC)) = x)
#define SET_UIVR_2(x) (*((CHAR *)(MBAR + 0x1F0)) = x)
#define READ_UMR1_2() (*((CHAR *)(MBAR + 0x1C0)))
#define READ_UMR2_2() (*((CHAR *)(MBAR + 0x1C0)))
#define READ_USR_2() (*((CHAR *)(MBAR + 0x1C4)))
#define READ_URB_2() (*((CHAR *)(MBAR + 0x1CC)))
#define READ_UIPCR_2() (*((CHAR *)(MBAR + 0x1D0)))
#define READ_UISR_2() (*((CHAR *)(MBAR + 0x1D4)))
#define READ_UIVR_2() (*((CHAR *)(MBAR + 0x1F0)))
#define READ_UIP_2() (*((CHAR *)(MBAR + 0x1F4)))
/* Macros for reading and writing the UART2 control registers */
#define SET2_UMR1_2(x) (*((CHAR *)(MBAR + 0x200)) = x)
#define SET2_UMR2_2(x) (*((CHAR *)(MBAR + 0x200)) = x)
#define SET2_UCSR_2(x) (*((CHAR *)(MBAR + 0x204)) = x)
#define SET2_UCR_2(x) (*((CHAR *)(MBAR + 0x208)) = x)
#define SET2_UTB_2(x) (*((CHAR *)(MBAR + 0x20C)) = x)
#define SET2_UACR_2(x) (*((CHAR *)(MBAR + 0x210)) = x)
#define SET2_UIMR_2(x) (*((CHAR *)(MBAR + 0x214)) = x)
#define SET2_UBG1_2(x) (*((CHAR *)(MBAR + 0x218)) = x)
#define SET2_UBG2_2(x) (*((CHAR *)(MBAR + 0x21C)) = x)
#define SET2_UIVR_2(x) (*((CHAR *)(MBAR + 0x230)) = x)
#define READ2_UMR1_2() (*((CHAR *)(MBAR + 0x200)))
#define READ2_UMR2_2() (*((CHAR *)(MBAR + 0x200)))
#define READ2_USR_2() (*((CHAR *)(MBAR + 0x204)))
#define READ2_URB_2() (*((CHAR *)(MBAR + 0x20C)))
#define READ2_UIPCR_2() (*((CHAR *)(MBAR + 0x210)))
#define READ2_UISR_2() (*((CHAR *)(MBAR + 0x214)))
#define READ2_UIVR_2() (*((CHAR *)(MBAR + 0x230)))
#define READ2_UIP_2() (*((CHAR *)(MBAR + 0x234)))
/* Defines for fields and bits of UART control registers */
#define UMR1_PARITY_NONE 0x10
#define UMR1_PARITY_EVEN 0x00
#define UMR1_PARITY_ODD 0x04
#define UMR1_DATA_BITS_6 0x01
#define UMR1_DATA_BITS_7 0x02
#define UMR1_DATA_BITS_8 0x03
#define UMR2_MODE_NORMAL 0x00
#define UMR2_MODE_AUTO_ECHO 0x40
#define UMR2_MODE_LOCAL_LOOP 0x80
#define UMR2_MODE_REMOTE_LOOP 0xC0
#define UMR2_STOP_BITS_1 0x07
#define UMR2_STOP_BITS_2 0x0F
#define UCR_RST_MODE_REG 0x10
#define UCR_RST_RX 0x20
#define UCR_RST_TX 0x30
#define UCR_RST_ERR_STAT 0x40
#define UCR_TX_ENABLE 0x04
#define UCR_TX_DISABLE 0x08
#define UCR_RX_ENABLE 0x01
#define UCR_RX_DISABLE 0x02
#define UCSR_TIMER 0xDD
#define UIVR_VECTOR 64
#define UIVR_VECTOR2 65
#define UIMR_RX_ENABLE 0x02
#define UIMR_TX_ENABLE 0x01
#define UIMR_DISABLE 0x00
#define USR_RECV_BREAK 0x80
#define USR_FRAME_ERR 0x40
#define USR_PARITY_ERR 0x20
#define USR_OVERRUN 0x10
#define USR_TXRDY 0x04
#define USR_RXRDY 0x01
#define UBG_1200 0x028B
#define UBG_2400 0x0145
#define UBG_4800 0x00A2
#define UBG_9600 0x0051
#define UBG_19200 0x0028
#define UBG_28800 0x001B
#define UBG_33600 0x0017
#define UBG_56000 0x000E
#define UART1 1
#define UART2 2
/* Defines to be used by application */
#define PARITY_NONE UMR1_PARITY_NONE
#define PARITY_EVEN UMR1_PARITY_EVEN
#define PARITY_ODD UMR1_PARITY_ODD
#define DATA_BITS_6 UMR1_DATA_BITS_6
#define DATA_BITS_7 UMR1_DATA_BITS_7
#define DATA_BITS_8 UMR1_DATA_BITS_8
#define MODE_NORMAL UMR2_MODE_NORMAL
#define MODE_AUTO_ECHO UMR2_MODE_AUTO_ECHO
#define MODE_LOCAL_LOOP UMR2_MODE_LOCAL_LOOP
#define MODE_REMOTE_LOOP UMR2_MODE_REMOTE_LOOP
#define STOP_BITS_1 UMR2_STOP_BITS_1
#define STOP_BITS_2 UMR2_STOP_BITS_2
#define UART_INVALID_PARITY -1
#define UART_INVALID_DATA_BITS -2
#define UART_INVALID_STOP_BITS -3
#define UART_INVALID_BAUD -4
#define UART_INVALID_COM_PORT -5
#define UART_INVALID_MODE -6
typedef struct UART_INIT_STRUCT
{
unsigned com_port;
unsigned data_bits;
unsigned stop_bits;
unsigned parity;
unsigned baud_rate;
unsigned data_mode;
unsigned vect;
} UART_INIT;
#define BUFFER_SIZE 4096
#define UART_BUFFER_FULL -1
#define UART_BUFFER_DATA -2
#define UART_BUFFER_EMPTY -3
typedef struct UART_BUFFER_STRUCT
{
char *head;
char *tail;
char *read;
char *write;
INT status;
char buffer[BUFFER_SIZE];
} UART_BUFFER;
#endif
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