📄 init.s
字号:
;
;/* Define extern function references. */
;
;VOID init_crc32(VOID);
;ULONG crc32(UCHAR *buf,INT len);
;ULONG test_ram(ULONG addr,ULONG len);
XREF _init_crc32
XREF _crc32
XREF STKTOP
XREF _main
SECTION .bss
;-------------------------------------------------------------
;Test Product Output Flag
;ULONG _Test_Product_Flag
XDEF _Test_Product_Flag
_Test_Product_Flag:
DS.B 4
XDEF _CPU_FLAG
_CPU_FLAG:
DS.L 1
;-------------------------------------------------------------
MBAR_ADDR EQU $30000000 ; Base address of all internal regs
CTRL_CODE_ADDR EQU $101E0000 ; CTRL Address in Flash , for 2MB flash ,2002.4.24
CTRL_CODE_ADDR1 EQU $002e0000 ; CTRL Address in,DRAM for VIA,2002.4.24,wuyujun
CTRL_CODE_ADDR2 EQU $002e0434 ; CTRL CODE begin Address in DRAM
CTRL_CODE_LEN EQU $1fff0 ; CTRL Length 128K
CTRL_CODE_CRC EQU $101FFFF0 ; CTRL Code CRC address
;MAIN_CODE_ADDR EQU $00350000 ; MAIN Address in DRAM
FLASH_BASE_ADDR EQU $10000000 ; Base address of flash
;FLASH_LENGTH EQU $100000
FLASH_LENGTH EQU $200000 ; flash length 2MB for using in vt6526, wuyujun
CACR EQU $002 ; Cache Control Register
CACHE_INV EQU $01000000 ; Value to invalidate entire cache
CACHE_EN EQU $80000000 ; Value to enable the cache
ISRAM_ADDR EQU $40000000 ; isram base address
ISRAM_CODE_LEN EQU $1800 ; 6K
ISRAM_LEN_1 EQU $2000 ; 8K
;AL300_ADDRESS EQU $50000000 ; AL300A registers base addr
;MAC_ADDRESS_ADDR EQU $10003FF0 ; MAC_ADDRESS
TMR1_1 EQU $100 ; Offset of Timer 1 Mode Register
TRR1_1 EQU $104 ; Offset of Timer 1 Reference Reg
TER1_1 EQU $111 ; Offset of Timer 1 Event Register
ICR9_1 EQU $1c ; Offset of Timer 1 Int Control Reg
TCN1 EQU $10c ; tcn1
TMR1_CFG EQU $0d ; Value to configure Timer 1
;1d - enable interrupt , 0d - disable interrupt.
TRR1_LOAD EQU $ffff ; Value to be compared to counter
TER1_CLEAR EQU $ff ; Value to clear timer interrupt
ICR9_CFG EQU $8f ; timer 1 int : level 3, pri 3
TIMER1_10MS_COUNT EQU $61a8 ; 10ms
;
;;;;add;;;;;;;;
ACR0 EQU $004
ACR1 EQU $005
ISRAM_LEN_2 EQU $1000 ; 4K 5307
TMR1_2 EQU $140 ; Offset of 5307 Timer 0 Mode Register
TRR1_2 EQU $144 ; Offset of 5307 Timer 0 Reference Reg
TER1_2 EQU $151 ; Offset of 5307 Timer 0 Event Register
ICR9_2 EQU $4d ; Offset of 5307 Timer 0 Int Control Reg
;
SECTION .sdata2
ALIGN 2
XDEF _INT_Vectors
_INT_Vectors:
DC.L STKTOP-4 ; Initial stack value 0
DC.L start ; System entry location 1
XDEF _INT_Version
_INT_Version:
ASCII "STAR-SWITCH-BOOT"
ASCII "01-01-01 "
ASCII "2002-06-28 \0"
DC.L 0
SECTION .text
XDEF _INT_Initialize
XDEF start
_INT_Initialize:
start:
;VOID INT_Initialize(void)
;{
; // Initialize temporary stack pointer
MOVE.L #___SP_INIT,A7
; // Initialize a5 to sdata (provided by linker)
; MOVE.L #__SDA_BASE_,A5 ; ---> no need
;
; // Lockout interrupts during initialization.
MOVE.W #$2700,SR
; --> VBR的初始化
MOVE.L A7,D1
MOVE.L #0,D0
MOVEA.L D0,A7
MOVEC.L A7,VBR
MOVEA.L D1,A7
; // init neccesary register: MBAR, RAMBAR, CS0, DRAM
MOVE.L #$30000001,D0 ; NOT using MBAR_ADDR
MOVEC.L D0,MBAR
MOVE.L #$40000001,D0
MOVEC.L D0,RAMBAR
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ICR
;;;;;; ;_Get_CPU_Type;;;;;;;;;;;;;;
MOVE.L #0,D0
MOVE.B (MBAR_ADDR+$14),D0
CMP.L #$04,D0
BNE _CMP_END
MOVE.B (MBAR_ADDR+$15),D0
CMP.L #$08,D0
BNE _CMP_END
MOVE.B (MBAR_ADDR+$16),D0
CMP.L #$0C,D0
BNE _CMP_END
MOVE.L #0,D0
JMP _CMP_CON1
_CMP_END:
MOVE.L #1,D0
_CMP_CON1:
;move.l #0,d0 ;add jcb ls
CMP.L #0,D0
BNE _INIT_5307_1
;;;;;;;;5206;;;;;;;;;;;;;;;;;;;;;;;;
MOVE.L #0x0,D0 ;0x0
MOVE.B D0,(MBAR_ADDR+$3) ;SIMR
MOVE.L #0x85,D0 ;
MOVE.B D0,(MBAR_ADDR+$14) ;
MOVE.L #0x8B,D0 ;
MOVE.B D0,(MBAR_ADDR+$15) ;
MOVE.L #0x8E,D0 ;
MOVE.B D0,(MBAR_ADDR+$16) ;
MOVE.L #0x92,D0 ;
MOVE.B D0,(MBAR_ADDR+$17) ;
MOVE.L #0x95,D0 ;
MOVE.B D0,(MBAR_ADDR+$18) ;
MOVE.L #0x98,D0 ;
MOVE.B D0,(MBAR_ADDR+$19) ;
MOVE.L #0x9F,D0 ;
MOVE.B D0,(MBAR_ADDR+$1A) ;
MOVE.L #0x1E,D0 ;
MOVE.B D0,(MBAR_ADDR+$1B) ;
MOVE.L #0x97,D0 ;
MOVE.B D0,(MBAR_ADDR+$1C) ;
MOVE.L #0x96,D0 ;
MOVE.B D0,(MBAR_ADDR+$1D) ;
MOVE.L #0x8C,D0 ;
MOVE.B D0,(MBAR_ADDR+$1E) ;
MOVE.L #0x8E,D0 ;
MOVE.B D0,(MBAR_ADDR+$1F) ;
MOVE.L #0x8D,D0 ;
MOVE.B D0,(MBAR_ADDR+$20) ;
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+0x36) ;IMR
MOVE.W #0x300,D0 ; SET PARALLEL PORT, NOT BDM DEBUG MODE
MOVE.W D0,(MBAR_ADDR+0xCA) ;PAR
MOVE.L #$0,D0 ;SET ALL TO ZERO
MOVE.B D0,(MBAR_ADDR+$1C9) ;PPDAT =1
MOVE.L #$ff,D0 ;SET DIRECT TO OUTPUT
MOVE.B D0,(MBAR_ADDR+$1C5) ;PADDR
; // Initialize chip select registers
MOVE.L #$1000,D0 ; CS0
MOVE.W D0,(MBAR_ADDR+$64) ; CSAR0
MOVE.L #$1F0000,D0
MOVE.L D0,(MBAR_ADDR+$68) ; CSMR0 flash size = 0x100000
;MOVE.L #$3D83,D0 ; WS = 15?
MOVE.L #$1593,D0 ; WS = 5,5*25ns=125ns,ASET=1,Address Setup 1 Clock
MOVE.W D0,(MBAR_ADDR+$6E) ; CSCR0
MOVE.L #$3DC0,D0
MOVE.W D0,(MBAR_ADDR+$7A) ;cs1 disable
MOVE.L #0x5000,D0 ;CS2
MOVE.W D0,(MBAR_ADDR+0x7c) ;CSAR2
MOVE.L #0x0,D0
MOVE.L D0,(MBAR_ADDR+0x80) ;CSMR2
MOVE.L #0x118f,D0
MOVE.W D0,(MBAR_ADDR+0x86) ;CSCR2
;MOVE.L #0x5000,D0 ;CS3 --> AL300A
;MOVE.W D0,(MBAR_ADDR+0x88) ;CSAR3
;MOVE.L #0x0,D0
;MOVE.L D0,(MBAR_ADDR+0x8C) ;CSMR3
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+0x92) ;CSCR3
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; MOVE.L #AL300_ADDRESS,A0
; MOVE.L #0,(A0) ;D0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+0x9E) ;CSCR4
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+0xAA) ;CSCR5
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+0xB6) ;CSCR6
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+0xC2) ;CSCR7
MOVE.L #0x0300,D0
MOVE.W D0,(MBAR_ADDR+0xC6) ;DMCR
; // init DRAM controller
;MOVE.L #$0,D0
MOVE.L #$27,D0
MOVE.W D0,(MBAR_ADDR+$46) ; DCRR
MOVE.L #$D020,D0
MOVE.W D0,(MBAR_ADDR+$4A) ; DCTR
MOVE.L #$0,D0
MOVE.W D0,(MBAR_ADDR+$4C) ; DCAR0
MOVE.L #$FE0000,D0
MOVE.L D0,(MBAR_ADDR+$50) ; DCMR0 DRAM size = 0x400000
MOVE.L #$27,D0
MOVE.B D0,(MBAR_ADDR+$57) ; DCCR0
; Cache
MOVE.L #CACHE_INV,D1 ; pick up Invalidate All command
MOVEC D1,CACR ; invalidate all cache lines
MOVE.L #CACHE_EN,D1 ; pick up Enable command
MOVEC D1,CACR ; enable the cache
; /* Set up Timer 1 for a 10ms periodic tick */
;
MOVE.L #ICR9_CFG,D0 ; Pick up configuration value for ICR9
MOVE.B D0,(MBAR_ADDR+ICR9_1) ; Setup Timer 1 interrupt for lev 3, pri 3
MOVE.L #TRR1_LOAD,D0 ; Pick up compare value
MOVE.W D0,(MBAR_ADDR+TRR1_1) ; Load into TRR1, val = (40MHz / 16) / 100
MOVE.L #TMR1_CFG,D0 ; Pick up configuration value for TMR1
MOVE.W D0,(MBAR_ADDR+TMR1_1) ; Setup Timer 1
; Prescaler = 0
; Disable reference interrupt
; Restart timer after reference reached
; System clock / 16
; Enable timer
; // Init UART
JSR _Init_UART_1
MOVE.L #12000000,D0 ;delay 600ms
jbsr _DELAY
MOVE.L #$1,D0 ;SET ALL TO ZERO
MOVE.B D0,(MBAR_ADDR+$1C9) ;PPDAT =1
JSR _Init_UART_1
MOVE.L #1200000,D0 ;delay 60ms
jbsr _DELAY
MOVE.L #$9,D0 ;SET ALL TO ZERO
MOVE.B D0,(MBAR_ADDR+$1C9) ;PPDAT =1
MOVE.L #0,D0
MOVE.L D0,_CPU_FLAG
JMP _CON1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;5307;;;;;;;;;;;;;;;;;;;;;;;;;
_INIT_5307_1:
; Cache
MOVE.L #CACHE_INV,D0 ; pick up Invalidate All command
MOVEC D0,CACR
move.l #0xA1000300,D0 ;enable cache, invalidate it,
;default mode is cache-inhibited imprecise
movec D0, CACR
; move.l #0x0000C000,D0 ;cache SDRAM space, enable,
;ignore FC2, cacheable, writethrough
; movec D0,ACR0
; move.l #0x1000C000,D0 ;cache FLASH space, enable,
;ignore FC2, cacheable, writethrough
; movec D0,ACR1
; // init SDRAM controller
; //Power-Up Sequence:
MOVE.W #$801F,D0
MOVE.W D0,(MBAR_ADDR+$100) ; DCR
MOVE.L #$1304,D0
MOVE.L D0,(MBAR_ADDR+$108) ; DACR0
MOVE.L #$3FC0001,D0
MOVE.L D0,(MBAR_ADDR+$10C) ; DMR0
; //Precharge Sequence:
move.l #$130c, d0 ;Set DACR0[IP]
move.l d0, (MBAR_ADDR+$108)
move.l #$DEADBEEF, d0
move.l d0, $00000400
; //Refresh Sequence:
move.l #0x9304, d0 ;Enable refresh bit in DACR0
move.l d0, (MBAR_ADDR+$108)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ICR
; MOVE.L #0x0FFFFFFFF,D0 ;Clear all pending interrupts
; MOVE.W D0,(MBAR_ADDR+0x40) ;IPR read only
MOVE.L #$00,D0 ;
MOVE.B D0,(MBAR_ADDR+$4C) ;
MOVE.L #$00,D0 ;
MOVE.B D0,(MBAR_ADDR+$4D) ;
MOVE.L #$00,D0 ;
MOVE.B D0,(MBAR_ADDR+$4E) ;
MOVE.L #$00,D0 ;
MOVE.B D0,(MBAR_ADDR+$4F) ;
MOVE.L #$00,D0 ;
MOVE.B D0,(MBAR_ADDR+$50) ;
MOVE.L #$00,D0 ;
MOVE.B D0,(MBAR_ADDR+$51) ;
MOVE.L #$00,D0
MOVE.B D0,(MBAR_ADDR+$52) ;
MOVE.L #$00,D0
MOVE.B D0,(MBAR_ADDR+$53) ;
MOVE.L #$00,D0
MOVE.B D0,(MBAR_ADDR+$54) ;
MOVE.L #$00,D0
MOVE.B D0,(MBAR_ADDR+$55) ;
MOVE.L #$FFFFFFFE,D0 ;Mask all interrupt sources
MOVE.L D0,(MBAR_ADDR+0x44) ;IMR
MOVE.L #$00,D0
MOVE.B D0,(MBAR_ADDR+$01) ;Disable the Software Watchdog
MOVE.W #$FFFF,D0 ; SET PARALLEL PORT, NOT BDM DEBUG MODE
MOVE.W D0,(MBAR_ADDR+0x4) ;PAR
; // Initialize chip select registers
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+$8C) ;CSAR1
MOVE.L D0,(MBAR_ADDR+$90) ;cs1 disable,CSMR valid = 0
MOVE.W D0,(MBAR_ADDR+$96) ;CSCR1
MOVE.L #0x5000,D0 ;CS2
MOVE.W D0,(MBAR_ADDR+$98) ;CSAR2
MOVE.L #0x1580,D0
MOVE.W D0,(MBAR_ADDR+$A2) ;CSCR2
MOVE.L #0x1,D0
MOVE.L D0,(MBAR_ADDR+$9C) ;CSMR2,valid = 1
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+$A4) ;CSAR3
MOVE.L D0,(MBAR_ADDR+$A8) ;CSMR3
MOVE.W D0,(MBAR_ADDR+$AE) ;CSCR3
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+$B0) ;CSAR4
MOVE.L D0,(MBAR_ADDR+$B4) ;CSMR4
MOVE.W D0,(MBAR_ADDR+$BA) ;CSCR4
MOVE.L #0x0,D0
MOVE.W D0,(MBAR_ADDR+$BC) ;CSAR5
MOVE.L D0,(MBAR_ADDR+$C0) ;CSMR5
MOVE.W D0,(MBAR_ADDR+$C6) ;CSCR5
;; MOVE.L #0x0,D0
MOVE.L #0x6000,D0
MOVE.W D0,(MBAR_ADDR+$C8) ;CSAR6
MOVE.L #0x0D60,D0
MOVE.W D0,(MBAR_ADDR+$D2) ;CSCR6
MOVE.L #0x10001,D0
MOVE.L D0,(MBAR_ADDR+$CC) ;CSMR6
MOVE.L #0x0,D0
MOVE.L #0x7000,D0
MOVE.W D0,(MBAR_ADDR+$D4) ;CSAR7
MOVE.L #0x0D60,D0
MOVE.W D0,(MBAR_ADDR+$DE) ;CSCR7
MOVE.L #0x10001,D0
MOVE.L D0,(MBAR_ADDR+$D8) ;CSMR7
MOVE.L #$1000,D0 ; CS0
MOVE.W D0,(MBAR_ADDR+$80) ; CSAR0
MOVE.L #$0DA0,D0 ; WS = 3,AA=1,PS=16bit port size,
; BEM=1,BSTR=0,BSTW=0
MOVE.W D0,(MBAR_ADDR+$8A) ; CSCR0
MOVE.L #$1F0001,D0
MOVE.L D0,(MBAR_ADDR+$84) ; CSMR0 flash size = 0x200000,valid = 1
move.l #0x9344, d0 ;Finish the configuration by issuing the IMRS.
move.l d0, (MBAR_ADDR+$108)
move.l #0xDEADBEEF, d0 ;Write to memory location to init. precharge
move.l d0, 0x400
; /* Set up Timer 1 for a 10ms periodic tick */
;
MOVE.L #ICR9_CFG,D0 ; Pick up configuration value for ICR9
MOVE.B D0,(MBAR_ADDR+ICR9_2) ; Setup Timer 1 interrupt for lev 3, pri 3
MOVE.L #TRR1_LOAD,D0 ; Pick up compare value
MOVE.W D0,(MBAR_ADDR+TRR1_2) ; Load into TRR1, val = (40MHz / 16) / 100
MOVE.L #TMR1_CFG,D0 ; Pick up configuration value for TMR1
MOVE.W D0,(MBAR_ADDR+TMR1_2) ; Setup Timer 1
; Prescaler = 0
; Disable reference interrupt
; Restart timer after reference reached
; System clock / 16
; Disable timer
; move.l #0x00600001, d0 ;Mask bit 19 of address
; move.l d0, (MBAR_ADDR+$10C)
move.l #$6000FFFF,a0
move.l #$0,d0
move.b (a0),d0
move.l #$7000FFFF,a0
move.l #$0,d0
move.b (a0),d0
; // Init UART
JSR _Init_UART_2
MOVE.L #600000,D0 ;delay 600ms
jbsr _DELAY
;RESET MAC&PHY
move.l #$60000000,a0
move.l #$0,d0
move.b (a0),d0
MOVE.L #60000,D0 ;delay 60ms
jbsr _DELAY
move.l #$70000000,a0
move.l #$0,d0
move.b (a0), d0
MOVE.L #1,D0
MOVE.L D0,_CPU_FLAG
_CON1:
;delay 1s
MOVEQ.L #0,D1
MOVE.L D1,_Test_Product_Flag
MOVEQ.L #0,D7
.L2:
TST.L D7
BEQ .L3
; // Send BOOT Version Message
MOVE.L #_BOOT_Version_Msg,A0
;Not in debug,don't send msg,2001/4/22,comment
JSR _BOOT_Send_Msg
.L3:
; // DRAM test
JSR _test_dram ; call test_dram()
CMP.L #0, D0 ; 0 ---> success
BNE _DRAM_Error
TST.L D7
BEQ .L4
MOVE.L #_Test_Dram_Passed_Msg,A0
JSR _BOOT_Send_Msg
.L4:
; // ISRAM test
JSR _test_isram ; call test_isram()
CMP.L #0, D0 ; 0 ---> success
BNE _ISRAM_Error
TST.L D7
BEQ .L5
MOVE.L #_Test_Isram_Passed_Msg,A0
JSR _BOOT_Send_Msg
.L5:
; // Init crc32_table
JSR _init_crc32
; // Check Ctrl CRC
MOVE.L #CTRL_CODE_ADDR,A0 ; A0 = CTRL ADDRESS in flash
MOVE.L (A0)+,D1 ; CRC
MOVE.L (4,A0),D0 ; TSIZE
ADDI.L #28,D0
CMP.L #CTRL_CODE_LEN,D0
JGT _CTRL_Error
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