seg7_1.map.eqn

用VHTL描述7段数码管器

--c[0] is c[0]
c[0]_reg_input = VCC;
c[0] = TFFE(c[0]_reg_input, GLOBAL(clk), , !reset, );


--A1L52 is clk~6
A1L52_or_out = GLOBAL(clk);
A1L52 = A1L52_or_out;


--c[1] is c[1]
c[1]_or_out = c[0];
c[1]_reg_input = c[1]_or_out;
c[1] = TFFE(c[1]_reg_input, GLOBAL(clk), , !reset, );


--c[2] is c[2]
c[2]_p1_out = c[1] & c[0];
c[2]_or_out = c[2]_p1_out;
c[2]_reg_input = c[2]_or_out;
c[2] = TFFE(c[2]_reg_input, GLOBAL(clk), , !reset, );


--B1L1 is seg7_2:u1|b[0]~63
B1L1_or_out = c[1];
B1L1 = c[2] $ B1L1_or_out;


--B1L3 is seg7_2:u1|b[3]~67
B1L3_p1_out = !c[1] & c[0];
B1L3_or_out = !c[2];
B1L3 = B1L3_p1_out $ B1L3_or_out;


--B1L6 is seg7_2:u1|b[5]~72
B1L6_p1_out = !c[1] & !c[0];
B1L6_or_out = B1L6_p1_out # !c[2];
B1L6 = B1L6_or_out;


--B1L21 is seg7_2:u1|clkout[5]~69
B1L21_p1_out = !c[2] & !c[0];
B1L21_or_out = B1L21_p1_out;
B1L21 = B1L21_or_out;


--B1L31 is seg7_2:u1|clkout[5]~71
B1L31_p1_out = !c[1] & !c[2] & !c[0];
B1L31_or_out = B1L31_p1_out;
B1L31 = !(B1L31_or_out);


--B1L11 is seg7_2:u1|clkout[4]~74
B1L11_p1_out = !c[1] & !c[2] & c[0];
B1L11_or_out = B1L11_p1_out;
B1L11 = !(B1L11_or_out);


--B1L01 is seg7_2:u1|clkout[3]~77
B1L01_p1_out = c[1] & !c[2] & !c[0];
B1L01_or_out = B1L01_p1_out;
B1L01 = !(B1L01_or_out);


--B1L9 is seg7_2:u1|clkout[2]~80
B1L9_p1_out = c[1] & !c[2] & c[0];
B1L9_or_out = B1L9_p1_out;
B1L9 = !(B1L9_or_out);


--B1L8 is seg7_2:u1|clkout[1]~83
B1L8_p1_out = !c[0] & c[2] & !c[1];
B1L8_or_out = B1L8_p1_out;
B1L8 = !(B1L8_or_out);


--B1L7 is seg7_2:u1|clkout[0]~86
B1L7_p1_out = c[0] & c[2] & !c[1];
B1L7_or_out = B1L7_p1_out;
B1L7 = !(B1L7_or_out);


--B1L5 is seg7_2:u1|b[4]~75
B1L5_p1_out = !c[2] & c[0];
B1L5_or_out = B1L5_p1_out # !c[1];
B1L5 = B1L5_or_out;


--B1L2 is seg7_2:u1|b[1]~78
B1L2_p1_out = !c[2] & c[0];
B1L2_or_out = B1L2_p1_out # c[1];
B1L2 = !(B1L2_or_out);


--B1L4 is seg7_2:u1|b[3]~84
B1L4_p1_out = c[2] & c[1];
B1L4_p2_out = c[2] & !c[0];
B1L4_p3_out = !c[2] & !c[1] & c[0];
B1L4_or_out = B1L4_p1_out # B1L4_p2_out # B1L4_p3_out;
B1L4 = !(B1L4_or_out);


--clk is clk
--operation mode is input

clk = INPUT();


--reset is reset
--operation mode is input

reset = INPUT();


--a[0] is a[0]
--operation mode is output

a[0] = OUTPUT(c[0]);


--ld1 is ld1
--operation mode is output

ld1 = OUTPUT(A1L52);


--a[1] is a[1]
--operation mode is output

a[1] = OUTPUT(c[1]);


--a[2] is a[2]
--operation mode is output

a[2] = OUTPUT(c[2]);


--b[5] is b[5]
--operation mode is output

b[5] = OUTPUT(B1L6);


--b[3] is b[3]
--operation mode is output

b[3] = OUTPUT(B1L3);


--b[2] is b[2]
--operation mode is output

b[2] = OUTPUT(B1L21);


--b[0] is b[0]
--operation mode is output

b[0] = OUTPUT(B1L1);


--b[6] is b[6]
--operation mode is output

b[6] = OUTPUT(B1L4);


--b[4] is b[4]
--operation mode is output

b[4] = OUTPUT(B1L5);


--b[1] is b[1]
--operation mode is output

b[1] = OUTPUT(B1L2);


--clkout[5] is clkout[5]
--operation mode is output

clkout[5] = OUTPUT(B1L31);


--clkout[4] is clkout[4]
--operation mode is output

clkout[4] = OUTPUT(B1L11);


--clkout[3] is clkout[3]
--operation mode is output

clkout[3] = OUTPUT(B1L01);


--clkout[2] is clkout[2]
--operation mode is output

clkout[2] = OUTPUT(B1L9);


--clkout[1] is clkout[1]
--operation mode is output

clkout[1] = OUTPUT(B1L8);


--clkout[0] is clkout[0]
--operation mode is output

clkout[0] = OUTPUT(B1L7);