seg7_1.map.qmsg

用VHTL描述7段数码管器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 17 16:07:35 2006 " "Info: Processing started: Wed May 17 16:07:35 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off seg7_1 -c seg7_1 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off seg7_1 -c seg7_1" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7_1.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file seg7_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7_2-seg7_2_arch " "Info: Found design unit 1: seg7_2-seg7_2_arch" {  } { { "e:/chengxu/seg7_1/seg7_1.vhd" "seg7_2-seg7_2_arch" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 seg7_1-seg7_1_arch " "Info: Found design unit 2: seg7_1-seg7_1_arch" {  } { { "e:/chengxu/seg7_1/seg7_1.vhd" "seg7_1-seg7_1_arch" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 45 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7_2 " "Info: Found entity 1: seg7_2" {  } { { "e:/chengxu/seg7_1/seg7_1.vhd" "seg7_2" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 3 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 seg7_1 " "Info: Found entity 2: seg7_1" {  } { { "e:/chengxu/seg7_1/seg7_1.vhd" "seg7_1" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 35 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin clk to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "36 " "Info: Implemented 36 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "17 " "Info: Implemented 17 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 17 16:07:38 2006 " "Info: Processing ended: Wed May 17 16:07:38 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}