seg7_1.tan.qmsg

用VHTL描述7段数码管器

{ "Info" "ITDB_FULL_TCO_RESULT" "clk clkout\[0\] c\[0\] 17.000 ns register " "Info: tco from clock clk to destination pin clkout\[0\] through register c\[0\] is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns c\[0\] 2 REG LC14 17 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC14; Fanout = 17; REG Node = 'c\[0\]'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "0.000 ns" { clk c[0] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "3.000 ns" { clk c[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c\[0\] 1 REG LC14 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC14; Fanout = 17; REG Node = 'c\[0\]'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "" { c[0] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns seg7_2:u1\|clkout\[0\]~86 2 COMB LC49 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC49; Fanout = 1; COMB Node = 'seg7_2:u1\|clkout\[0\]~86'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "9.000 ns" { c[0] seg7_2:u1|clkout[0]~86 } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns clkout\[0\] 3 PIN PIN_41 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'clkout\[0\]'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "4.000 ns" { seg7_2:u1|clkout[0]~86 clkout[0] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "13.000 ns" { c[0] seg7_2:u1|clkout[0]~86 clkout[0] } "NODE_NAME" } } }  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "3.000 ns" { clk c[0] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "13.000 ns" { c[0] seg7_2:u1|clkout[0]~86 clkout[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk ld1 15.000 ns Longest " "Info: Longest tpd from source pin clk to destination pin ld1 is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns clk~6 2 COMB LC45 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC45; Fanout = 1; COMB Node = 'clk~6'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "8.000 ns" { clk clk~6 } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns ld1 3 PIN PIN_25 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'ld1'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "4.000 ns" { clk~6 ld1 } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 93.33 % " "Info: Total cell delay = 14.000 ns ( 93.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 6.67 % " "Info: Total interconnect delay = 1.000 ns ( 6.67 % )" {  } {  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "15.000 ns" { clk clk~6 ld1 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk a\[0\] c\[0\] 8.000 ns register " "Info: Minimum tco from clock clk to destination pin a\[0\] through register c\[0\] is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns c\[0\] 2 REG LC14 17 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC14; Fanout = 17; REG Node = 'c\[0\]'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "0.000 ns" { clk c[0] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "3.000 ns" { clk c[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c\[0\] 1 REG LC14 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC14; Fanout = 17; REG Node = 'c\[0\]'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "" { c[0] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns a\[0\] 2 PIN PIN_5 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'a\[0\]'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "4.000 ns" { c[0] a[0] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "4.000 ns" { c[0] a[0] } "NODE_NAME" } } }  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "3.000 ns" { clk c[0] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "4.000 ns" { c[0] a[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk ld1 15.000 ns Shortest " "Info: Shortest tpd from source pin clk to destination pin ld1 is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns clk~6 2 COMB LC45 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC45; Fanout = 1; COMB Node = 'clk~6'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "8.000 ns" { clk clk~6 } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns ld1 3 PIN PIN_25 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'ld1'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "4.000 ns" { clk~6 ld1 } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 93.33 % " "Info: Total cell delay = 14.000 ns ( 93.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 6.67 % " "Info: Total interconnect delay = 1.000 ns ( 6.67 % )" {  } {  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "15.000 ns" { clk clk~6 ld1 } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 17 16:07:47 2006 " "Info: Processing ended: Wed May 17 16:07:47 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}