seg7_1.tan.qmsg

用VHTL描述7段数码管器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 17 16:07:47 2006 " "Info: Processing started: Wed May 17 16:07:47 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off seg7_1 -c seg7_1 " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off seg7_1 -c seg7_1" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 39 -1 0 } } { "e:/xuexiruanjian/shudian/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/xuexiruanjian/shudian/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register c\[0\] register c\[2\] 76.92 MHz 13.0 ns Internal " "Info: Clock clk has Internal fmax of 76.92 MHz between source register c\[0\] and destination register c\[2\] (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns c\[0\] 1 REG LC14 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC14; Fanout = 17; REG Node = 'c\[0\]'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "" { c[0] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns c\[2\] 2 REG LC11 17 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC11; Fanout = 17; REG Node = 'c\[2\]'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "8.000 ns" { c[0] c[2] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "8.000 ns" { c[0] c[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns c\[2\] 2 REG LC11 17 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC11; Fanout = 17; REG Node = 'c\[2\]'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "0.000 ns" { clk c[2] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "3.000 ns" { clk c[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns c\[0\] 2 REG LC14 17 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC14; Fanout = 17; REG Node = 'c\[0\]'" {  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "0.000 ns" { clk c[0] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "3.000 ns" { clk c[0] } "NODE_NAME" } } }  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "3.000 ns" { clk c[2] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "3.000 ns" { clk c[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "e:/chengxu/seg7_1/seg7_1.vhd" "" "" { Text "e:/chengxu/seg7_1/seg7_1.vhd" 58 -1 0 } }  } 0}  } { { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "8.000 ns" { c[0] c[2] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "3.000 ns" { clk c[2] } "NODE_NAME" } } } { "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" "" "" { Report "e:/chengxu/seg7_1/db/seg7_1_cmp.qrpt" Compiler "seg7_1" "UNKNOWN" "V1" "e:/chengxu/seg7_1/db/seg7_1.quartus_db" { Floorplan "" "" "3.000 ns" { clk c[0] } "NODE_NAME" } } }  } 0}