seg7_1.hier_info

用VHTL描述7段数码管器

|seg7_1
a[0] <= c[0].DB_MAX_OUTPUT_PORT_TYPE
a[1] <= c[1].DB_MAX_OUTPUT_PORT_TYPE
a[2] <= c[2].DB_MAX_OUTPUT_PORT_TYPE
b[0] <= seg7_2:u1.b[0]
b[1] <= seg7_2:u1.b[1]
b[2] <= seg7_2:u1.b[2]
b[3] <= seg7_2:u1.b[3]
b[4] <= seg7_2:u1.b[4]
b[5] <= seg7_2:u1.b[5]
b[6] <= seg7_2:u1.b[6]
clk => c[1].CLK
clk => c[0].CLK
clk => c[2].CLK
clk => ld1.DATAIN
clkout[0] <= seg7_2:u1.clkout[0]
clkout[1] <= seg7_2:u1.clkout[1]
clkout[2] <= seg7_2:u1.clkout[2]
clkout[3] <= seg7_2:u1.clkout[3]
clkout[4] <= seg7_2:u1.clkout[4]
clkout[5] <= seg7_2:u1.clkout[5]
reset => c[1].PRESET
reset => c[0].PRESET
reset => c[2].PRESET
ld1 <= clk.DB_MAX_OUTPUT_PORT_TYPE


|seg7_1|seg7_2:u1
a[0] => Mux~0.IN10
a[0] => Mux~1.IN10
a[0] => Mux~2.IN10
a[0] => Mux~3.IN5
a[0] => Mux~4.IN10
a[0] => Mux~6.IN10
a[0] => Mux~7.IN10
a[0] => Mux~8.IN10
a[0] => Mux~9.IN10
a[0] => Mux~10.IN10
a[0] => Mux~11.IN10
a[1] => Mux~0.IN9
a[1] => Mux~1.IN9
a[1] => Mux~2.IN9
a[1] => Mux~4.IN9
a[1] => Mux~5.IN5
a[1] => Mux~6.IN9
a[1] => Mux~7.IN9
a[1] => Mux~8.IN9
a[1] => Mux~9.IN9
a[1] => Mux~10.IN9
a[1] => Mux~11.IN9
a[2] => Mux~0.IN8
a[2] => Mux~1.IN8
a[2] => Mux~2.IN8
a[2] => Mux~3.IN4
a[2] => Mux~4.IN8
a[2] => Mux~5.IN4
a[2] => Mux~6.IN8
a[2] => Mux~7.IN8
a[2] => Mux~8.IN8
a[2] => Mux~9.IN8
a[2] => Mux~10.IN8
a[2] => Mux~11.IN8
b[0] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
b[1] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
b[2] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
b[3] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
b[4] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
b[5] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
b[6] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
clkout[0] <= Mux~11.DB_MAX_OUTPUT_PORT_TYPE
clkout[1] <= Mux~10.DB_MAX_OUTPUT_PORT_TYPE
clkout[2] <= Mux~9.DB_MAX_OUTPUT_PORT_TYPE
clkout[3] <= Mux~8.DB_MAX_OUTPUT_PORT_TYPE
clkout[4] <= Mux~7.DB_MAX_OUTPUT_PORT_TYPE
clkout[5] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE