📄 seg7_1.fit.rpt
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+-----------------------------------------------+
; Output Pin Load For Reported TCO ;
+--------------+-------+------------------------+
; I/O Standard ; Load ; Termination Resistance ;
+--------------+-------+------------------------+
; LVTTL ; 10 pF ; Not Available ;
; LVCMOS ; 10 pF ; Not Available ;
; TTL ; 0 pF ; Not Available ;
+--------------+-------+------------------------+
+----------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |seg7_1 ; 17 ; 23 ; |seg7_1 ;
; |seg7_2:u1| ; 13 ; 0 ; |seg7_1|seg7_2:u1 ;
+----------------------------+------------+------+---------------------+
+----------------------------------------------------------------------------------------+
; Control Signals ;
+-------+----------+---------+--------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-------+----------+---------+--------+--------+----------------------+------------------+
; clk ; PIN_83 ; 4 ; Clock ; yes ; On ; -- ;
; reset ; PIN_1 ; 3 ; Preset ; no ; -- ; -- ;
+-------+----------+---------+--------+--------+----------------------+------------------+
+---------------------------------------------------------------------+
; Global & Other Fast Signals ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; clk ; PIN_83 ; 4 ; On ; -- ;
+------+----------+---------+----------------------+------------------+
+----------------------------------+
; Non-Global High Fan-Out Signals ;
+------------------------+---------+
; Name ; Fan-Out ;
+------------------------+---------+
; c[0] ; 15 ;
; c[2] ; 14 ;
; c[1] ; 14 ;
; reset ; 3 ;
; seg7_2:u1|b[3]~84 ; 1 ;
; seg7_2:u1|b[1]~78 ; 1 ;
; seg7_2:u1|b[4]~75 ; 1 ;
; seg7_2:u1|clkout[0]~86 ; 1 ;
; seg7_2:u1|clkout[1]~83 ; 1 ;
; seg7_2:u1|clkout[2]~80 ; 1 ;
; seg7_2:u1|clkout[3]~77 ; 1 ;
; seg7_2:u1|clkout[4]~74 ; 1 ;
; seg7_2:u1|clkout[5]~71 ; 1 ;
; seg7_2:u1|clkout[5]~69 ; 1 ;
; seg7_2:u1|b[5]~72 ; 1 ;
; seg7_2:u1|b[3]~67 ; 1 ;
; seg7_2:u1|b[0]~63 ; 1 ;
; clk~6 ; 1 ;
+------------------------+---------+
+-----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 11 / 288 ( 3 % ) ;
; PIAs ; 11 / 288 ( 3 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 1.38) ; Number of LABs (Total = 4) ;
+----------------------------------------------+-----------------------------+
; 0 ; 4 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 2.13) ; Number of LABs (Total = 4) ;
+----------------------------------------+-----------------------------+
; 0 ; 4 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 1 ;
+----------------------------------------+-----------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC8 ; c[2], c[1], c[0] ; b[6] ;
; A ; LC5 ; c[2], c[0], c[1] ; b[4] ;
; A ; LC6 ; c[1], c[0], c[2] ; b[5] ;
; A ; LC3 ; c[1], c[0], c[2] ; b[3] ;
; A ; LC11 ; clk, c[1], c[0], reset ; a[2], seg7_2:u1|b[0]~63, seg7_2:u1|b[3]~67, seg7_2:u1|b[5]~72, seg7_2:u1|clkout[5]~69, seg7_2:u1|clkout[5]~71, seg7_2:u1|clkout[4]~74, seg7_2:u1|clkout[3]~77, seg7_2:u1|clkout[2]~80, seg7_2:u1|clkout[1]~83, seg7_2:u1|clkout[0]~86, seg7_2:u1|b[4]~75, seg7_2:u1|b[1]~78, seg7_2:u1|b[3]~84 ;
; A ; LC13 ; clk, c[0], reset ; a[1], c[2], seg7_2:u1|b[0]~63, seg7_2:u1|b[3]~67, seg7_2:u1|b[5]~72, seg7_2:u1|clkout[5]~71, seg7_2:u1|clkout[4]~74, seg7_2:u1|clkout[3]~77, seg7_2:u1|clkout[2]~80, seg7_2:u1|clkout[1]~83, seg7_2:u1|clkout[0]~86, seg7_2:u1|b[4]~75, seg7_2:u1|b[1]~78, seg7_2:u1|b[3]~84 ;
; A ; LC14 ; clk, reset ; a[0], c[1], c[2], seg7_2:u1|b[3]~67, seg7_2:u1|b[5]~72, seg7_2:u1|clkout[5]~69, seg7_2:u1|clkout[5]~71, seg7_2:u1|clkout[4]~74, seg7_2:u1|clkout[3]~77, seg7_2:u1|clkout[2]~80, seg7_2:u1|clkout[1]~83, seg7_2:u1|clkout[0]~86, seg7_2:u1|b[4]~75, seg7_2:u1|b[1]~78, seg7_2:u1|b[3]~84 ;
; B ; LC25 ; c[2], c[1] ; b[0] ;
; B ; LC29 ; c[2], c[0] ; b[2] ;
; B ; LC27 ; c[2], c[0], c[1] ; b[1] ;
; C ; LC45 ; clk ; ld1 ;
; D ; LC59 ; c[1], c[2], c[0] ; clkout[5] ;
; D ; LC57 ; c[1], c[2], c[0] ; clkout[4] ;
; D ; LC56 ; c[1], c[2], c[0] ; clkout[3] ;
; D ; LC53 ; c[1], c[2], c[0] ; clkout[2] ;
; D ; LC51 ; c[0], c[2], c[1] ; clkout[1] ;
; D ; LC49 ; c[0], c[2], c[1] ; clkout[0] ;
+-----+------------+------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Wed May 17 16:07:41 2006
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off seg7_1 -c seg7_1
Info: Selected device EPM7128SLC84-15 for design seg7_1
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Wed May 17 16:07:42 2006
Info: Elapsed time: 00:00:01
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