seg7_1.vhd

用VHTL描述7段数码管器

library IEEE;             --底层文件
use IEEE.std_logic_1164.all;
entity seg7_2 is
  port(
     a:in std_logic_vector (2 downto 0);
     b:out std_logic_vector (6 downto 0);
     clkout:out std_logic_vector(5 downto 0)
  );
end seg7_2;
architecture seg7_2_arch of seg7_2 is
begin
  process(a)
  begin
    case a is
     when "000"=> b <= "1111110"; 
                 clkout<="011111";--0
     when "001"=> b <= "0110000";
                 clkout<="101111"; --1
     when "010"=> b <= "1101101"; 
                 clkout<="110111";--2
     when "011"=> b <= "1111001"; 
                 clkout<="111011";--3
     when "100"=> b <= "0110011"; 
                 clkout<="111101";--4
     when "101"=> b <= "1011011"; 
                clkout<="111110";--5
     when others=> b <= "0000000";
                clkout<="111111";
    end case;
   end process;
end;
library IEEE;             --顶层文件
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity seg7_1 is
  port(
   a:out std_logic_vector(2 downto 0);--把a设置为输出变量
   b:out std_logic_vector(6 downto 0) ;
   clk:in std_logic;
   clkout:out std_logic_vector(5 downto 0);
   reset:in std_logic;
   ld1:out std_logic
   );
end seg7_1;
architecture seg7_1_arch of seg7_1 is
component seg7_2
port(
   a:in std_logic_vector (2 downto 0);
   b:out std_logic_vector (6 downto 0);
   clkout:out std_logic_vector(5 downto 0) 
   );
end component;
signal c:std_logic_vector (2 downto 0);
begin
 u1: seg7_2 port map(a=>c,b=>b,clkout=>clkout);--把变量a换成信号c传递
 process(clk,reset)
   begin
    if(reset='1')then
          c<="111";
    elsif(clk'event and clk='1')then
          c<=c+1;
    end if;  
 end process;
 a<=c;--把信号c赋值给a,作为输出
ld1<=clk;
end;