otg_hal.h

一个USB主机核的驱动程序

*	This Read-only bit is set when the core is acting as a Host.
**************************************************/

#define	DevCtl_rw_HostReq				(1 << 1)
/**************************************************
*	When set, the core will initiate the Host Negotiation when Suspend mode is entered. It is
*	cleared when Host Negotiation is completed. See Section 15. (‘B’ device onl
**************************************************/

#define	DevCtl_rw_Session				(1 << 0)
/**************************************************
*	When operating as an ‘A’ device, this bit is set or cleared by the CPU to start or end a session.
*	When operating as a ‘B’ device, this bit is set/cleared by the core when a session starts/ends.
*	It is also set by the CPU to initiate the Session Request Protocol, or cleared by the CPU when in
*	Suspend mode to perform a software disconnect. Note: Clearing this bit when the core is not
*	suspended will result in undefined behavior.
**************************************************/




#define	TxFIFOsz_rw_DPB					(1 << 4)
#define	RxFIFOsz_rw_DPB					(1 << 4)
/**************************************************
*	Defines whether double-packet buffering supported. When ‘1’, double-packet buffering is
*	supported. When ‘0’, only single-packet buffering is supporte
**************************************************/


/* ULPI register */
typedef struct _ULPI_REG
{
	BYTE	CarKitCtrl;
	BYTE	VBusCtrl;
	BYTE	IntSrc;
	BYTE	IntMask;
	BYTE	RegAddr;
	BYTE	RegData;
	BYTE	RawData;
	BYTE	RegCtrl;
}ULPI_REG;


/* Additional config register */
typedef struct _CONFIG_REG
{
	BYTE	EPInfo;
/**************************************************
*	EPInfo		address:78h, Reset value:Implementation dependent
*	This 8-bit read-only register allows read-back of the number of Tx and Rx endpoints included in the design.
**************************************************/
	BYTE	RAMInfo;
/**************************************************
*	RAMInfo		address:79h, Reset value:Implementation dependent
*	This 8-bit read-only register provides information about the width of the RAM and the number of DMA channels.
**************************************************/
	BYTE	LinkInfo;
/**************************************************
*	LinkInfo		address:7Ah, Reset value:8'h5C
*	This 8-bit register allows some delays to be specified.
**************************************************/
	BYTE	VPLen;
/**************************************************
*	VPLen		address:7Bh, Reset value:8'h3C
*	This 8-bit register sets the duration of the VBus pulsing charge.
**************************************************/
	BYTE	HS_EOF;
/**************************************************
*	HS_EOF		address:7Ch, Reset value:8'h80
*	This 8-bit register sets the minimum time gap that is to be allowed between the start of the last transaction and the EOF for
*	High-speed transactions.
**************************************************/
	BYTE	FS_EOF;
/**************************************************
*	FS_EOF		address:7Dh, Reset value:8'h77
*	This 8-bit register sets the minimum time gap that is to be allowed between the start of the last transaction and the EOF for
*	Full-speed transactions.
**************************************************/
	BYTE	LS_EOF;
/**************************************************
*	LS_EOF		address:7Eh, Reset value:8'h72
*	This 8-bit register sets the minimum time gap that is to be allowed between the start of the last transaction and the EOF for
*	Low-speed transactions.
**************************************************/
	BYTE	reserved;
}CONFIG_REG; 


/*
 * DMA control register
 */
typedef struct _DMA_CTRL
{
	DWORD	Intr;
	DWORD	Ctrl;
	DWORD	Addr;
	DWORD	Count;
}DMA_CTRL;


typedef enum _OTG_ERROR
{
	OTG_NO_ERR = 0,
	RX_STALL,
	ERROR,
	NAK
	
}OTG_ERROR;

 /* OTG register map, OTG spec page 8 */
#define	OTG_REG_ADDR				0x9C00	
/* define OTG register map for debug */
typedef struct _OTG_REG
{
	COMMON_USB_REG 	CommonUSB;
	CSR_REG 		IndexedCSR;
	DWORD			EndpointFIFO[16];
	CTRL_FIFO_REG 	CtrlFIFO;
	ULPI_REG		ULPI;
	CONFIG_REG 		Config;
	BYTE			reserved1[128];
	CSR_REG			CSR[16];
	DMA_CTRL		DMAChl;
	BYTE			reserved2[240];			/* reserved for DMA channel */
	DWORD			RqPktCount[16];		/* RqPktCount[0] do not care for endpoint 0 */
}OTG_REG;


/*--------------------------------------------------------------------------------------------*/

/*
 *	FAddr			address:00h, Reset value:8'h00 
 *	FAddr is an 8-bit register that should be written with the 7-bit address of the peripheral part of the transaction.
 *	When the core is being used in Host mode (DevCtl.D2=1), this register should be set to the value sent in a SET _ADDRESS
 *	command during device enumeration as the address for the peripheral device.
 *	When the core is being used in Peripheral mode (DevCtl.D2=0), this register should be written with the address received through a
 *	SET_ADDRESS command, which will then be used for decoding the function address in subsequent token packets. Note: The new
 *	address will not take effect immediately as the host will still be using the old address for the Status stage of the device request. The
 *	core will continue to use the old address for decoding packets until the device request has completed.
 */
#define	otg_CommonUSB_FAddr			((volatile BYTE XDATA *)(OTG_REG_ADDR + 0x00))

/*
 *	Power			address:01h, Reset value:8'h20 
 *	Power is an 8-bit register that is used for controlling Suspend and Resume signaling, 
 *	and some basic operational aspects of the core.
 */
#define	otg_CommonUSB_Power			((volatile BYTE XDATA *)(OTG_REG_ADDR + 0x01))

/*
 *	IntrTx			address:02h, Reset value:16'h0000 
 *	IntrTx is a 16-bit read-only register that indicates which interrupts are currently active for Endpoint 0 and the Tx Endpoints 1–15.
 *	Note: Bits relating to endpoints that have not been configured will always return 0. Note also that all active interrupts are cleared
 *	when this register is read.
 */
#define	otg_CommonUSB_IntrTx		((volatile WORD XDATA *)(OTG_REG_ADDR + 0x02))

/*
 *	IntrRx			address:04h, Reset value:16'h0000 
 *	IntrRx is an 16-bit read-only register that indicates which of the interrupts for Rx Endpoints 1 – 15 are currently active. Note: Bits
 *	relating to endpoints that have not been configured will always return 0. Note also that all active interrupts are cleared when this
 *	register is read.
 */
#define	otg_CommonUSB_IntrRx		((volatile WORD XDATA *)(OTG_REG_ADDR + 0x04))

/*
 *	IntrTxE			address:06h, Reset value:16'hFFFF masked with the Tx endpoints implemented
 *	IntrTxE is a 16-bit register that provides interrupt enable bits for the interrupts in IntrTx. Where a bit is set to 1, MC_NINT will
 *	be asserted on the corresponding interrupt in the IntrTx register becoming set. Where a bit is set to 0, the interrupt in IntrTx is still set
 *	but MC_NINT is not asserted. On reset, the bits corresponding to Endpoint 0 and the Tx endpoints included in the design are set to
 *	1, while the remaining bits are set to 0. Note: Bits relating to endpoints that have not been configured will always return 0.
 */
#define	otg_CommonUSB_IntrTxEn		((volatile WORD XDATA *)(OTG_REG_ADDR + 0x06))

/*
 *	IntrRxE			address:08h, Reset value:16'hFFFE masked with the Rx endpoints implemented
 *	IntrRxE is a 16-bit register that provides interrupt enable bits for the interrupts in IntrRx. Where a bit is set to 1, MC_NINT will
 *	be asserted on the corresponding interrupt in the IntrRx register becoming set. Where a bit is set to 0, the interrupt in IntrTx is still set
 *	but MC_NINT is not asserted. On reset, the bits corresponding to the Rx endpoints included in the design are set to 1, while the
 *	remaining bits are set to 0. Note: Bits relating to endpoints that have not been configured will always return 0.
 */
#define	otg_CommonUSB_IntrRxEn		((volatile WORD XDATA *)(OTG_REG_ADDR + 0x08))

/*
 *	IntrUSB			address:0Ah, Reset value:8'h00
 *	IntrUSB is an 8-bit read-only register that indicates which USB interrupts are currently active. 
 *	All active interrupts will be cleared when this register is read.
 */
#define	otg_CommonUSB_IntrUSB		((volatile BYTE XDATA *)(OTG_REG_ADDR + 0x0A))

/*
 *	IntrUSBE		address:0Bh, Reset value:8'h06
 *	IntrUSBE is an 8-bit register that provides interrupt enable bits for each of the interrupts in IntrUSB.
 */	
#define	otg_CommonUSB_IntrUSBE		((volatile BYTE XDATA *)(OTG_REG_ADDR + 0x0B))

/*
 *	Frame		address:0Ch, Reset value:16'h0000
 *	Frame is a 16-bit register that holds the last received frame number.
 */	
#define	otg_CommonUSB_Frame			((volatile WORD XDATA *)(OTG_REG_ADDR + 0x0C))

/*
 *	Index		address:0Eh, Reset value:8'h00
 *	Each Tx endpoint and each Rx endpoint have their own set of control/status registers located between 100h – 1FFh. In addition one
 *	set of Tx control/status and one set of Rx control/status registers appear at 10h – 19h. Index is a 4-bit register that
 *	determines which endpoint control/status registers are accessed.
 */	
#define	otg_CommonUSB_Index			((volatile BYTE XDATA *)(OTG_REG_ADDR + 0x0E))

/* 
 *	TestMode	address:0Fh, Reset value:8'h00
 *	Testmode is an 8-bit register that is primarily used to put the core into one of the four test modes for High-speed operation
 *	described in the USB 2.0 specification – in response to a SET FEATURE: TESTMODE command. It is not used in norma
 *	operation.
 */
#define	otg_CommonUSB_TestMode		((volatile BYTE XDATA *)(OTG_REG_ADDR + 0x0F))


/*-------------------------------------------------------------------------------------------------*/

/*
 *	TxMaxP		address:10h, Reset value:16'h0000
 *	The TxMaxP register defines the maximum amount of data that can be transferred through the selected Tx endpoint in a single
 *	operation. There is a TxMaxP register for each Tx endpoint (except Endpoint 0).
 *
 *	Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is
 *	subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in Fullspeed
 *	and High-speed operations.
 *
 *	Where the option of High-bandwidth Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints has been taken
 *	when the core is configured, the register includes either 2 or 5 further bits that define a multiplier m which is equal to one more than
 *	the value recorded.
 */
#define	otg_IndexedCSR_TxMaxP		((volatile WORD XDATA *)(OTG_REG_ADDR + 0x10))

/*
 *	CSR0		address:12h, Reset value:16'h0000
 *	CSR0 is a 16-bit register that provides control and status bits for Endpoint 0. Note: The interpretation of the register depends on
 *	whether the core is acting as a peripheral or as a host. Users should also be aware that the value returned when the register is
 *	read reflects the status attained e.g. as a result of writing to the register.
 */
#define	otg_IndexedCSR_CSR0			((volatile WORD XDATA *)(OTG_REG_ADDR + 0x12))

/*
 *	TxCSR		address:12h, Reset value:16'h0000
 *	TxCSR is a 16-bit register that provides control and status bits for transfers through the currently-selected Tx endpoint. There is a
 *	TxCSR register for each co