otg_hal.h

一个USB主机核的驱动程序

*			(ii) This bit has no efect where the endpoint is being used for Isochronous tran sfers.
**************************************************/

#define	RxCSR_ps_FlushFIFO				(1 << 4)
/**************************************************
*	The CPU writes a 1 to this bit to flush the next packet to be read from the endpoint Rx FIFO.
*	The FIFO pointer is reset and the RxPktRdy bit (below) is cleared. 
*	Note: FlushFIFO should only be used when RxPktRdy is set. At other times, it may cause data to be corrupted. Also note that, if the
*	FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO..
**************************************************/

#define	RxCSR_pr_DataError				(1 << 3)
/**************************************************
*	This bit is set when RxPktRdy is set if the data packet has a CRC or bit-stuff error. It is cleared
*	when RxPktRdy is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk
*	mode, it always returns zero.
**************************************************/

#define	RxCSR_prc_OverRun				(1 << 2)
/**************************************************
*	This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit.
*	Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero.
**************************************************/

#define	RxCSR_pr_FIFOFull				(1 << 1)
/**************************************************
*	This bit is set when no more packets can be loaded into the Rx FIFO.
**************************************************/

#define	RxCSR_prc_RxPktRdy				(1 << 0)
/**************************************************
*	This bit is set when a data packet has been received. The CPU should clear this bit when the packet
*	has been unloaded from the Rx FIFO. An interrupt is generated when the bit is set.
**************************************************/


#define	RxCSR_hrw_AutoClear				(1 << 15)
/**************************************************
*	If the CPU sets this bit then the RxPktRdy bit will be automatically cleared when a packet of
*	RxMaxP bytes has been unloaded from the Rx FIFO. When packets of less than the maximum
*	packet size are unloaded, RxPktRdy will have to be cleared manually. 
*	Note: Should not be set for high-bandwidth Isochronous endpoints.
**************************************************/

#define	RxCSR_hrw_AutoReq				(1 << 14)
/**************************************************
*	If the CPU sets this bit, the ReqPkt bit will be automatically set when the RxPktRdy bit is cleared.
*	Note: This bit is automatically cleared when a short packet is received.
**************************************************/

#define	RxCSR_hrw_DMAReqEnab			(1 << 13)
/**************************************************
*	The CPU sets this bit to enable the DMA request for the Rx endpoint.
**************************************************/

#define	RxCSR_hr_PIDError				(1 << 12)
/**************************************************
*	ISO Transactions Only: The core sets this bit to indicate a PID error in the received packet.
*	Bulk/Interrupt Transactions: The setting of this bit is ignored.
**************************************************/

#define	RxCSR_hrw_DMAReqMode			(1 << 11)
/**************************************************
*	The CPU sets this bit to select DMA Mode 1 and clears this bit to select DMA Mode 0. 
*	Note: This bit should not be cleared in the same cycle as RxPktRdy is cleared.
**************************************************/

#define	RxCSR_hrc_IncompRx				(1 << 8)
/**************************************************
*	This bit will be set in a high-bandwidth Isochronous/Interrupt transfer if the packet received is
*	incomplete. It will be cleared when RxPktRdy is cleared. 
*	Note: If USB protocols are folowed correctly, this bit should never be set. 
*	The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. 
*	(In anything other than a high-bandwidth transfer, this bit wil always return 0.)
**************************************************/

#define	RxCSR_hs_ClrDataTog				(1 << 7)
/**************************************************
*	The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
**************************************************/

#define	RxCSR_hrc_RxStall				(1 << 6)
/**************************************************
*	The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
**************************************************/

#define	RxCSR_hrw_ReqPkt				(1 << 5)
/**************************************************
*	The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RxPktRdy is set.
**************************************************/

#define	RxCSR_hs_FlushFIFO				(1 << 4)
/**************************************************
*	The CPU writes a 1 to this bit to flush the next packet to be read from the endpoint Rx FIFO.
*	The FIFO pointer is reset and the RxPktRdy bit (below) is cleared. 
*	Note: FlushFIFO should only be used when RxPktRdy is set. At other times, it may cause data to be corrupted. 
*	Also note that, if the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO.
**************************************************/

#define	RxCSR_hrc_DataError_NAKTimeout	(1 << 3)
/**************************************************
*	When operating in ISO mode, this bit is set when RxPktRdy is set if the data packet has a CRC or
*	bit-stuff error and cleared when RxPktRdy is cleared. In Bulk mode, this bit will be set when the Rx
*	endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK
*	Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue.
**************************************************/

#define	RxCSR_hrc_Error					(1 << 2)
/**************************************************
*	The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has
*	been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This
*	bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero.
**************************************************/

#define	RxCSR_hr_FIFOFull				(1 << 1)
/**************************************************
*	This bit is set when no more packets can be loaded into the Rx FIFO.
**************************************************/

#define	RxCSR_hrc_RxPktRdy				(1 << 0)
/**************************************************
*	This bit is set when a data packet has been received. The CPU should clear this bit when the packet
*	has been unloaded from the Rx FIFO. An interrupt is generated when the bit is set.
**************************************************/




#define	TxType_rw_Protocol				(3 << 4)
#define	TxType_Protocol_Illegal			(0 << 4)
#define	TxType_Protocol_Isochronous		(1 << 4)
#define	TxType_Protocol_Bulk			(2 << 4)
#define	TxType_Protocol_Interrupt		(3 << 4) 
/**************************************************
*	The CPU should set this to select the required protocol for the Tx endpoint:
*	00: Illegal
*	01: Isochronous
*	10: Bulk
*	11: Interrupt
**************************************************/	

#define	TxType_rw_TargetEndpointNumber	(15 << 0)
/**************************************************
*	The CPU should set this value to the endpoint number contained in the Tx endpoint descriptor
*	returned to the during device enumeration.
**************************************************/	




#define	RxType_rw_Protocol				(3 << 4)
#define	RxType_Protocol_Illegal			(0 << 4)
#define	RxType_Protocol_Isochronous		(1 << 4)
#define	RxType_Protocol_Bulk			(2 << 4)
#define	RxType_Protocol_Interrupt		(3 << 4) 
/**************************************************
*	The CPU should set this to select the required protocol for the Rx endpoint:
*	00: Illegal
*	01: Isochronous
*	10: Bulk
*	11: Interrupt
**************************************************/	

#define	RxType_rw_TargetEndpointNumber	(15 << 0)
/**************************************************
*	The CPU should set this value to the endpoint number contained in the Rx endpoint descriptor
*	returned to the during device enumeration.
**************************************************/	



/**************************************************
*	config bit define, see 2.3.3
**************************************************/	
#define	ConfigData_r_MPRxE				(1 << 7)
#define	ConfigData_r_MPTxE				(1 << 6)
#define	ConfigData_r_BigEndian			(1 << 5)
#define	ConfigData_r_HBRxE				(1 << 4)
#define	ConfigData_r_HBTxE				(1 << 3)
#define	ConfigData_r_DynFIFOSizing		(1 << 2)
#define	ConfigData_r_SoftConE			(1 << 1)
#define	ConfigData_r_UTMIDataWidth		(1 << 0)





/* Additional control and FIFO register */
typedef struct _CTRL_FIFO_REG
{
	BYTE	DevCtl;
/**************************************************
*	DevCtl		address:60h, Reset value:8'h80
*	DevCtl is an 8-bit register that is used to select whether the core is operating in Peripheral mode or in Host mode, and for
*	controlling and monitoring the USB VBus line.
**************************************************/
	BYTE	reserved1;
	BYTE	TxFIFOsz;
	BYTE	RxFIFOsz;
	WORD	TxFIFOadd;
	WORD	RxFIFOadd;
	DWORD	VControl_VStatus;		/* don't care */
	WORD	HWVers;
/**************************************************
*	HWVers		address:6Ch, Reset value:Version dependent
*	HWVers register is a 16-bit read-only register that returns information about the version of the RTL from which the core hardware
*	was generated, in particular the RTL version number (vxx.y).
**************************************************/
	BYTE	reserved2;
	BYTE	reserved3;
}CTRL_FIFO_REG;					



#define	DevCtl_r_B_Device				(1 << 7)
/**************************************************
*	This Read-only bit indicates whether the core is operating as the ‘A’ device or the ‘B’ device. 0 ?
*	‘A’ device; 1 ? ‘B’ device. Only valid while a session is in progr
*	Note: If the core is in Force_Host mode (i.e. a session has been started with Testmode.D7 = 1), this bit
*	will indicate the state of the HOSTDISCON input signal from the PHY.
*	Bit Name Function
**************************************************/

#define	DevCtl_r_FSDev					(1 << 6)
/**************************************************
*	This Read-only bit is set when a full-speed or high-speed device has been detected being connected to
*	the port. (High-speed devices are distinguished from full-speed by checking for high-speed chirps
*	when the device is reset.) Only valid in Host mode.
**************************************************/

#define	DevCtl_r_LSDev					(1 << 5)
/**************************************************
*	This Read-only bit is set when a low-speed device has been detected being connected to the port.
*	Only valid in Host mode.
**************************************************/

#define DevCtl_r_VBus					(3 << 3)
#define	DevCtl_VBus_bSE					(0 << 3)
#define	DevCtl_VBus_aSE_bAV				(1 << 3)
#define	DevCtl_VBus_aAV_bVBus			(2 << 3)
#define	DevCtl_VBus_aVBus				(3 << 3)
/**************************************************
These Read-only bits encode the current VBus level as follows:
*	D4 D3 Meaning
*	0 0 Below SessionEnd
*	0 1 Above SessionEnd, below AValid
*	1 0 Above AValid, below VBusValid
*	1 1 Above VBusValid
**************************************************/

#define	DevCtl_r_HostMode				(1 << 2)
/**************************************************