otg_hal.h

一个USB主机核的驱动程序

*	bit is cleared.
**************************************************/

#define	CSR0_hrc_RxPktRdy				(1 << 0)
/**************************************************
*	This bit is set when a data packet has been received. An interrupt is generated (if enabled) when
*	this bit is set. The CPU should clear this bit when the packet has been read from the FIFO.
**************************************************/




#define	TxCSR_prw_AutoSet				(1 << 15)
/**************************************************
*	If the CPU sets this bit, TxPktRdy will be automatically set when data of the maximum packet size
*	(value in TxMaxP) is loaded into the Tx FIFO. If a packet of less than the maximum packet size is
*	loaded, then TxPktRdy will have to be set manually. 
*	Note: Should not be set for either high-bandwidth Isochronous endpoints or high-bandwidth Interrupt endpoints.
**************************************************/

#define TxCSR_prw_ISO					(1 << 14)
/**************************************************
*	The CPU sets this bit to enable the Tx endpoint for Isochronous transfers, and clears it to enable
*	the Tx endpoint for Bulk or Interrupt transfers. 
*	Note: This bit only has any efect in Peripheral mode. In Host mode, it always returns zero.
**************************************************/

#define	TxCSR_prw_Mode					(1 << 13)
/**************************************************
*	The CPU sets this bit to enable the endpoint direction as Tx, and clears it to enable the endpoint
*	direction as Rx. 
*	Note: This bit only has any efect where the same endpoint FIFO is used for both Tx and Rx transactions.
**************************************************/

#define	TxCSR_prw_DMAReqEnab			(1 << 12)
/**************************************************
*	The CPU sets this bit to enable the DMA request for the Tx endpoint.
**************************************************/

#define	TxCSR_prw_FrcDataTog			(1 << 11)
/**************************************************
*	The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared
*	from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt Tx
*	endpoints that are used to communicate rate feedback for Isochronous endpoints.
**************************************************/

#define	TxCSR_prw_DMAReqMode			(1 << 10)
/**************************************************
*	The CPU sets this bit to select DMA Mode 1 and clears this bit to select DMA Mode 0.
*	Note: This bit must not be cleared either before or in the same cycle as the above DMAReqEnab bit is cleared.
**************************************************/

#define	TxCSR_prc_IncompTx				(1 << 7)
/**************************************************
*	When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is
*	set to indicate where a large packet has been split into 2 or 3 packets for transmission but
*	insufficient IN tokens have been received to send all the parts. 
*	Note: In anything other than a high-bandwidth transfer, this bit wil always return 0.
**************************************************/

#define	TxCSR_ps_ClrDataTog				(1 << 6)
/**************************************************
*	The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
**************************************************/

#define	TxCSR_prc_SentStall				(1 << 5)
/**************************************************
*	This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit
*	is cleared (see below). The CPU should clear this bit.
**************************************************/

#define	TxCSR_prw_SendStall				(1 << 4)
/**************************************************
*	The CPU writes a 1 to this bit to issue a STALL handshake to an IN token. The CPU clears this
*	bit to terminate the stall condition. 
*	Note:: (i) The FIFO should be flushed before SendStall is set. (ii) This bit
*	has no efect where the endpoint is being used for Isochronous transfers.
**************************************************/

#define	TxCSR_ps_FlushFIFO				(1 << 3)
/**************************************************
*	The CPU writes a 1 to this bit to flush the latest packet from the endpoint Tx FIFO. The FIFO pointer
*	is reset, the TxPktRdy bit (below) is cleared and an interrupt is generated. May be set simultaneously
*	with TxPktRdy to abort the packet that is currently being loaded into the FIFO. 
*	Note: FlushFIFO should only be used when TxPktRdy is set. At other times, it may cause data to be corrupted. Also note
*	that, if the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO.
**************************************************/

#define	TxCSR_prc_UnderRun				(1 << 2)
/**************************************************
*	The USB sets this bit if an IN token is received when the TxPktRdy bit not set. The CPU should
*	clear this bit.
**************************************************/

#define	TxCSR_prc_FIFONotEmpty			(1 << 1)
/**************************************************
*	The USB sets this bit when there is at least 1 packet in the Tx FIFO.
**************************************************/

#define	TxCSR_prs_TxPktRdy				(1 << 0)
/**************************************************
*	The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data
*	packet has been transmitted. An interrupt is also generated at this point (if enabled). TxPktRdy is also
*	automatically cleared prior to loading a second packet into a double-buffered FIFO.
**************************************************/


#define	TxCSR_hrw_AutoSet				(1 << 15)
/**************************************************
*	If the CPU sets this bit, TxPktRdy will be automatically set when data of the maximum packet size
*	(value in TxMaxP) is loaded into the Tx FIFO. If a packet of less than the maximum packet size is
*	loaded, then TxPktRdy will have to be set manually. 
*	Note: Should not be set for either high-bandwidth I sochronous endpoints or high-bandwidth Interrupt endpoints.
**************************************************/

#define	TxCSR_hrw_Mode					(1 << 13)
/**************************************************
*	The CPU sets this bit to enable the endpoint direction as Tx, and clears it to enable the endpoint direction
*	as Rx. 
*	Note: This bit only has any efect where the same endpoint FIFO is used for both Tx and Rx transactions.
**************************************************/

#define	TxCSR_hrw_DMAReqEnab			(1 << 12)
/**************************************************
*	The CPU sets this bit to enable the DMA request for the Tx endpoint.
**************************************************/

#define	TxCSR_hrw_FrcDataTog			(1 << 11)
/**************************************************
*	The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared
*	from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt Tx
*	endpoints that are used to communicate rate feedback for Isochronous endpoints.
**************************************************/

#define	TxCSR_hrw_DMAReqMode			(1 << 10)
/**************************************************
*	The CPU sets this bit to select DMA Mode 1 and clears this bit to select DMA Mode 0.
*	Note: This bit must not be cleared either before or in the same cycle as the above DMAReqEnab bit is cleared.
**************************************************/

#define	TxCSR_hrc_NAKTimeout_IncompTx	(1 << 7)
/**************************************************
*	Bulk endpoints only: This bit will be set when the Tx endpoint is halted following the receipt of
*	NAK responses for longer than the time set as the NAK Limit by the TxInterval register. The
*	CPU should clear this bit to allow the endpoint to continue.
*
*	High-bandwidth Interrupt endpoints only: This bit will be set if no response is received from the device to
*	which the packet is being sent.
**************************************************/

#define	TxCSR_hs_ClrDataTog				(1 << 6)
/**************************************************
*	The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
**************************************************/

#define	TxCSR_hrc_RxStall				(1 << 5)
/**************************************************
*	This bit is set when a STALL handshake is received. When this bit is set, any DMA request that is
*	in progress is stopped, the FIFO is completely flushed and the TxPktRdy bit is cleared (see below).
*	The CPU should clear this bit.
**************************************************/

#define	TxCSR_hs_FlushFIFO				(1 << 3)
/**************************************************
*	The CPU writes a 1 to this bit to flush the latest packet from the endpoint Tx FIFO. The FIFO pointer
*	is reset, the TxPktRdy bit (below) is cleared and an interrupt is generated. May be set simultaneously
*	with TxPktRdy to abort the packet that is currently being loaded into the FIFO. 
*	Note: FlushFIFO should only be used when TxPktRdy is set. At other times, it may cause data to be corrupted. Also note
*	that, if the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO.
**************************************************/

#define	TxCSR_hrc_Error					(1 << 2)
/**************************************************
*	The USB sets this bit when 3 attempts have been made to send a packet and no handshake packet has
*	been received. When the bit is set, an interrupt is generated, TxPktRdy is cleared and the FIFO
*	completely flushed. The CPU should clear this bit. Valid only when the endpoint is operating in Bulk or
*	Interrupt mode.
**************************************************/

#define	TxCSR_hrc_FIFONotEmpty			(1 << 1)
/**************************************************
*	The USB sets this bit when there is at least 1 packet in the Tx FIFO.
**************************************************/

#define	TxCSR_hrs_TxPktRdy				(1 << 0)
/**************************************************
*	The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data
*	packet has been transmitted. An interrupt is also generated at this point (if enabled). TxPktRdy is also
*	automatically cleared prior to loading a second packet into a double-buffered FIFO.
**************************************************/





#define	RxCSR_prw_AutoClear				(1 << 15)
/**************************************************
*	If the CPU sets this bit then the RxPktRdy bit will be automatically cleared when a packet of
*	RxMaxP bytes has been unloaded from the Rx FIFO. When packets of less than the maximum
*	packet size are unloaded, RxPktRdy will have to be cleared manually. 
*	Note: Should not be set for high-bandwidth Isochronous endpoints.
**************************************************/

#define	RxCSR_prw_ISO					(1 << 14)
/**************************************************
*	The CPU sets this bit to enable the Rx endpoint for Isochronous transfers, and clears it to enable
*	the Rx endpoint for Bulk/Interrupt transfers.
**************************************************/

#define	RxCSR_prw_DMAReqEnab			(1 << 13)
/**************************************************
*	The CPU sets this bit to enable the DMA request for the Rx endpoint.
**************************************************/

#define	RxCSR_prw_DisNyet_pr_PIDError	(1 << 12)
/**************************************************
*	Bulk/Interrupt Transactions: The CPU sets this bit to disable the sending of NYET handshakes.
*	When set, all successfully received Rx packets are ACK'd including at the point at which the FIFO
*	becomes full. Note: This bit only has any efect in High-speed mode, in which mode it should be set for al
*	Interrupt endpoints.
*
*	ISO Transactions: The core sets this bit to indicate a PID error in the received packet.
**************************************************/

#define	RxCSR_prw_DMAReqMode			(1 << 11)
/**************************************************
*	The CPU sets this bit to select DMA Mode 1 and clears this bit to select DMA Mode 0.
*	Note: This bit should not be cleared in the same cycle as RxPktRdy is cleared.
**************************************************/

#define	RxCSR_prc_IncompRx				(1 << 8)
/**************************************************
*	This bit is set in a high-bandwidth Isochronous/Interrupt transfer if the packet in the Rx FIFO is
*	incomplete because parts of the data were not received. It is cleared when RxPktRdy is cleared. 
*	Note: In anything other than a high-bandwidth transfer, this bit wil always return 0.
**************************************************/

#define	RxCSR_ps_ClrDataTog				(1 << 7)
/**************************************************
*	The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
**************************************************/

#define	RxCSR_prc_SentStall				(1 << 6)
/**************************************************
*	This bit is set when a STALL handshake is transmitted. The CPU should clear this bit.
**************************************************/

#define	RxCSR_prw_SendStall				(1 << 5)
/**************************************************
*	The CPU writes a 1 to this bit to issue a STALL handshake. The CPU clears this bit to terminate
*	the stall condition. 
*	Note:: (i) The FIFO should be flushed before SendStal is set.