otg_hal.h

一个USB主机核的驱动程序

/**************************************************
*	TestMode bit define, see 2.2.11
**************************************************/	
#define	TestMode_rw_ForceHost			(1 << 7)
#define	TestMode_rw_FIFOAccess			(1 << 6)
#define	TestMode_rw_ForceFS				(1 << 5)
#define	TestMode_rw_ForceHS				(1 << 4)
#define	TestMode_rw_Packet				(1 << 3)
#define	TestMode_rw_K					(1 << 2)
#define	TestMode_rw_J					(1 << 1)
#define	TestMode_rw_SE0_NAK				(1 << 0)




/* Indexed CSR register */
typedef struct _CSR_REG
{
	WORD	TxMaxP;
/**************************************************
*	TxMaxP		address:10h, Reset value:16'h0000
*	The TxMaxP register defines the maximum amount of data that can be transferred through the selected Tx endpoint in a single
*	operation. There is a TxMaxP register for each Tx endpoint (except Endpoint 0).
*
*	Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is
*	subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in Fullspeed
*	and High-speed operations.
*
*	Where the option of High-bandwidth Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints has been taken
*	when the core is configured, the register includes either 2 or 5 further bits that define a multiplier m which is equal to one more than
*	the value recorded.
**************************************************/
	WORD	CSR0_TxCSR;
/**************************************************
*	CSR0		address:12h, Reset value:16'h0000
*	CSR0 is a 16-bit register that provides control and status bits for Endpoint 0. Note: The interpretation of the register depends on
*	whether the core is acting as a peripheral or as a host. Users should also be aware that the value returned when the register is
*	read reflects the status attained e.g. as a result of writing to the register.
**************************************************/
/**************************************************
*	TxCSR		address:12h, Reset value:16'h0000
*	TxCSR is a 16-bit register that provides control and status bits for transfers through the currently-selected Tx endpoint. There is a
*	TxCSR register for each configured Tx endpoint (not including Endpoint 0). 
*	Note: The interpretation of the register depends on whether the core is acting as a peripheral or as a host. 
*	Users should also be aware that the value returned when the register is read reflects the status attained e.g. 
*	as a result of writing to the register.
**************************************************/
	WORD	RxMaxP;
/**************************************************
*	RxMaxP		address:14h, Reset value:16'h0000
*	The RxMaxP register defines the maximum amount of data that can be transferred through the selected Rx endpoint in a single
*	operation. There is a RxMaxP register for each Rx endpoint (except Endpoint 0).
*
*	Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is
*	subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in Fullspeed
*	and High-speed operations.
*
*	Where the option of High-bandwidth Isochronous/Interrupt endpoints or of combini ng Bulk packets has been taken when the core is
*	configured, the register includes either 2 or 5 further bits that define a multiplier m which is equal to one more than the value recorded.
**************************************************/
	WORD	RxCSR;
/**************************************************
*	RxCSR		address:16h, Reset value:16'h0000
*	RxCSR is an 16-bit register that provides control and status bits for transfers through the currently-selected Rx endpoint. There is an
*	RxCSR register for each configured Rx endpoint (not including Endpoint 0). 
*	Note: The interpretation of the register depends on whether the core is acting as a peripheral or as a host. 
*	Users should also be aware that the value returned when the register is read reflects the status attained e.g. as a result of writing to the register.
**************************************************/
	WORD	Count0_RxCount;
/**************************************************
*	Count0		address:18h, Reset value:7'b0000000
*	Count0 is a 7-bit read-only register that indicates the number of received data bytes in the Endpoint 0 FIFO. The value returned
*	changes as the contents of the FIFO change and is only valid while RxPktRdy (CSR0.D0) is set.
**************************************************/
/**************************************************
*	RxCount		address:18h, Reset value:13'b0000000000000
*	CRxCount is a 13-bit read-only register that holds the number of received data bytes in the packet currently in line to be read from the
*	Rx FIFO. If the packet was transmitted as multiple bulk packets, the number given will be for the combined packet. Note: The value
*	returned changes as the FIFO is unloaded and is only valid while RxPktRdy (RxCSR.D0) is set.
**************************************************/
	BYTE	TxType;
/**************************************************
*	TxType		address:1Ah, Reset value:8'h00(host mode only)
*	TxType is a 6-bit register that should be written with the endpoint number to be targeted by the endpoint in the lower 4 bits, and
*	the transaction protocol to use for the currently-selected Tx endpoint in the upper 2 bits.
*	There is a TxType register for each configured Tx endpoint (except Endpoint 0).
**************************************************/
	BYTE	NAKLimit0_TxInterval;
/**************************************************
*	NAKLimit0		address:1Bh, Reset value:5'b00000(host mode only)
*	NAKLimit0 is a 5-bit register that sets the number of frames/microframes (High-Speed transfers) after which Endpoint 0 should
*	timeout on receiving a stream of NAK responses. (Equivalent settings for other endpoints can be made through their TxInterval
*	and RxInterval registers: see Sections 2.3.11 and 2.3.13.)
*	The number of frames/microframes selected is 2(m-1) (where m is the value set in the register, valid values 2 – 16). If the host receives
*	NAK responses from the target for more frames than the number represented by the Limit set in this register, the endpoint will be
*	halted. Note: A value of 0 or 1 disables the NAK timeout function.
**************************************************/
/**************************************************
*	TxInterval		address:1Bh, Reset value:8'b00000000(host mode only)
*	TxInterval is an 8-bit register that, for Interrupt and Isochronous transfers, defines the polling interval for the currently-selected Tx
*	endpoint. For Bulk endpoints, this register sets the number of frames/microframes after which the endpoint should timeout on
*	receiving a stream of NAK responses. There is a TxInterval register for each configured Tx endpoint (except Endpoint 0).
**************************************************/
	BYTE	RxType;
/**************************************************
*	RxType		address:1Ch, Reset value:8'h00(host mode only)
*	RxType is a 6-bit register that should be written with the endpoint number to be targeted by the endpoint in the lower 4 bits, and
*	the transaction protocol to use for the currently-selected Rx endpoint in the upper 2 bits.
*	There is an RxType register for each configured Rx endpoint (except Endpoint 0).
**************************************************/
	BYTE	RxInterval;
/**************************************************
*	RxInterval		address:1Dh, Reset value:8'b00000000(host mode only)
*	RxInterval is an 8-bit register that, for Interrupt and Isochronous transfers, defines the polling interval for the currently-selected Rx
*	endpoint. For Bulk endpoints, this register sets the number of frames/microframes after which the endpoint should timeout on
*	receiving a stream of NAK responses. There is a RxInterval register for each configured Rx endpoint (except Endpoint 0).
**************************************************/
	BYTE	reserved;
	BYTE	ConfigData_FIFOSize;
/**************************************************
*	ConfigData		address:1Fh, Reset value:Configuration Dependent
*	ConfigData is an 8-bit Read-Only register that returns information about the selected core configuration.
**************************************************/
/**************************************************
*	FIFOSize		address:1Fh, Reset value:Configuration Dependent
*	FIFOSize is an 8-bit Read-Only register that returns the sizes of the FIFOs associated with the selected additional Tx/Rx endpoints.
*	The lower nibble encodes the size of the selected Tx endpoint FIFO; the upper nibble encodes the size of the selected Rx endpoint
*	FIFO. Values of 3 – 13 correspond to a FIFO size of 2n bytes (8 – 8192 bytes). If an endpoint has not been configured, a value of 0
*	will be displayed. Where the Tx and Rx endpoints share the same FIFO, the Rx FIFO size will be encoded as 0xF.
*	Note: The register only has this interpretation when the Index register is set to select one of Endpoints 1 – 15 and Dynamic Sizing
*	is not selected. It has a special interpretation when the Index register is set to select Endpoint 0 (see Section 2.3.3), while the result
*	returned is not valid where Dynamic FIFO sizing is used.
**************************************************/
}CSR_REG;


#define	CSR0_ps_FlushFIFO				(1 << 8)
/**************************************************
*	The CPU writes a 1 to this bit to flush the next packet to be transmitted/read from the
*	Endpoint 0 FIFO. The FIFO pointer is reset and the TxPktRdy/RxPktRdy bit (below) is
*	cleared. Note: FlushFIFO should only be used when TxPktRdy/RxPktRdy is set. At other
*	times, it may cause data to be corrupted.
**************************************************/

#define	CSR0_ps_ServicedSetupEnd		(1 << 7)
/**************************************************
*	The CPU writes a 1 to this bit to clear the SetupEnd bit. It is cleared automatically.
**************************************************/

#define	CSR0_ps_ServicedRxPktRdy		(1 << 6)
/**************************************************
*	The CPU writes a 1 to this bit to clear the RxPktRdy bit. It is cleared automatically.
**************************************************/

#define	CSR0_ps_SendStall				(1 << 5)
/**************************************************
*	The CPU writes a 1 to this bit to terminate the current transaction. The STALL handshake
*	will be transmitted and then this bit will be cleared automatically. 
*	Note: The FIFO should be flushed before SendStal is set.
**************************************************/

#define	CSR0_pr_SetupEnd				(1 << 4)
/**************************************************
*	This bit will be set when a control transaction ends before the DataEnd bit has been set.
*	An interrupt will be generated and the FIFO flushed at this time. The bit is cleared by
*	the CPU writing a 1 to the ServicedSetupEnd bit.
**************************************************/

#define	CSR0_ps_DataEnd					(1 << 3)
/**************************************************
*	The CPU sets this bit:
*	1. When setting TxPktRdy for the last data packet.
*	2. When clearing RxPktRdy after unloading the last data packet.
*	3. When setting TxPktRdy for a zero length data packet.
*	It is cleared automatically.
**************************************************/

#define	CSR0_prc_SentStall				(1 << 2)
/**************************************************
*	This bit is set when a STALL handshake is transmitted. The CPU should clear this bit.
**************************************************/

#define	CSR0_prs_TxPktRdy				(1 << 1)
/**************************************************
*	The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when the
* data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared.
**************************************************/

#define	CSR0_pr_RxPktRdy				(1 << 0)
/**************************************************
*	This bit is set when a data packet has been received. An interrupt is generated when this bit
*	is set. The CPU clears this bit by setting the ServicedRxPktRdy bit.
**************************************************/


#define	CSR0_hrw_DisPing				(1 << 11)
/**************************************************
*	The CPU writes a 1 to this bit to instruct the core not to issue PING tokens in data and status
*	phases of a high-speed Control transfer (for use with devices that do not respond to PING).
**************************************************/

#define	CSR0_hs_FlushFIFO				(1 << 8)
/**************************************************
*	The CPU writes a 1 to this bit to flush the next packet to be transmitted/read from the
*	Endpoint 0 FIFO. The FIFO pointer is reset and the TxPktRdy/RxPktRdy bit (below) is
*	cleared. Note: FlushFIFO should only be used when TxPktRdy/RxPktRdy is set. At other
*	times, it may cause data to be corrupted.
**************************************************/

#define	CSR0_hrc_NAKTimeout				(1 << 7)
/**************************************************
*	This bit will be set when Endpoint 0 is halted following the receipt of NAK responses for
*	longer than the time set by the NAKLimit0 register. The CPU should clear this bit to allow
*	the endpoint to continue.
**************************************************/

#define	CSR0_hrw_StatusPkt				(1 << 6)
/**************************************************
*	The CPU sets this bit at the same time as the TxPktRdy or ReqPkt bit is set, to perform a
*	status stage transaction. Setting this bit ensures that the data toggle is set to 1 so that a
*	DATA1 packet is used for the Status Stage transaction.
**************************************************/

#define	CSR0_hrw_ReqPkt					(1 << 5)
/**************************************************
*	The CPU sets this bit to request an IN transaction. It is cleared when RxPktRdy is set.
**************************************************/

#define	CSR0_hrc_Error					(1 << 4)
/**************************************************
*	This bit will be set when three attempts have been made to perform a transaction with no
*	response from the peripheral. The CPU should clear this bit. An interrupt is generated
*	when this bit is set.
**************************************************/

#define	CSR0_hrw_SetupPkt				(1 << 3)
/**************************************************
*	The CPU sets this bit, at the same time as the TxPktRdy bit is set, to send a SETUP token
*	instead of an OUT token for the transaction.
**************************************************/

#define	CSR0_hrc_RxStall				(1 << 2)
/**************************************************
*	This bit is set when a STALL handshake is received. The CPU should clear this bit.
**************************************************/

#define	CSR0_hrs_TxPktRdy				(1 << 1)
/**************************************************
*	The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically
*	when the data packet has been transmitted. An interrupt is generated (if enabled) when the