otg_hal.h

一个USB主机核的驱动程序

/****************************************************************
*                      MT View Silicon Tech. Inc.
*
*    Copyright 2007, MT View Silicon Tech. Inc., ShangHai, China
*                    All rights reserved.
*
*
* Filename:      	otg_hal.h
*
* Programmer:    	Grey
*
* Created: 	 		10/xx/2007
*
* Description: 		OTG hareware abstract layer head file
*					
*              
*****************************************************************/

#ifndef __OTG_HAL_H__
#define	__OTG_HAL_H__

#include "type.h"
#include "utility.h"


#define	DEBUG_EN		1


/* Define OTG access register */
#define	OTG_ACCESS_ADDR				0x9F20
#define	otg_op_status				((volatile BYTE XDATA *)(OTG_ACCESS_ADDR + 0))
#define	otg_rd_read_data			((volatile BYTE XDATA *)(OTG_ACCESS_ADDR + 1))
#define	utmi_src_sel_en				((volatile BYTE XDATA *)(OTG_ACCESS_ADDR + 2))
#define	utmi_src_sel				((volatile BYTE XDATA *)(OTG_ACCESS_ADDR + 3))

#define	OTG_STATUS_READ_OK			(1 << 0)
/**************************************************
*	Read only, when set read OTG register data ok.
**************************************************/

#define	OTG_READ_REQ				(1 << 1)
/**************************************************
*	Read only, when set re-read OTG register required, 
*	after read OTG_RD_READ_DATA reigster, this bit cleared auto.
**************************************************/

#define	OTG_WRITE_BUSY				(1 << 2)
/**************************************************
*	Read only, when write OTG register busy.
*	Note: Do not rd/wr OTG register until this bit is cleared.
**************************************************/

#define	OTG_UTMI_VBUSVALID			(1 << 0)
#define	OTG_UTMI_AVALID				(1 << 1)
#define	OTG_UTMI_SESSEND			(1 << 2)
#define	OTG_UTMI_IDDIG				(1 << 3)
#define	OTG_UTMI_HOST_DISCONN		(1 << 4)




/* common USB register */
typedef struct _COMMON_USB_REG
{
	BYTE	FAddr;					
/**************************************************
*	FAddr			address:00h, Reset value:8'h00 
*	FAddr is an 8-bit register that should be written with the 7-bit address of the peripheral part of the transaction.
*	When the core is being used in Host mode (DevCtl.D2=1), this register should be set to the value sent in a SET _ADDRESS
*	command during device enumeration as the address for the peripheral device.
*	When the core is being used in Peripheral mode (DevCtl.D2=0), this register should be written with the address received through a
*	SET_ADDRESS command, which will then be used for decoding the function address in subsequent token packets. Note: The new
*	address will not take effect immediately as the host will still be using the old address for the Status stage of the device request. The
*	core will continue to use the old address for decoding packets until the device request has completed.
**************************************************/
	BYTE	Power;					
/**************************************************
*	Power			address:01h, Reset value:8'h20 
*	Power is an 8-bit register that is used for controlling Suspend and Resume signaling, 
*	and some basic operational aspects of the core.
**************************************************/
	WORD	IntrTx;					
/**************************************************
*	IntrTx			address:02h, Reset value:16'h0000 
*	IntrTx is a 16-bit read-only register that indicates which interrupts are currently active for Endpoint 0 and the Tx Endpoints 1–15.
*	Note: Bits relating to endpoints that have not been configured will always return 0. Note also that all active interrupts are cleared
*	when this register is read.
**************************************************/
	WORD	IntrRx;					
/**************************************************
*	IntrRx			address:04h, Reset value:16'h0000 
*	IntrRx is an 16-bit read-only register that indicates which of the interrupts for Rx Endpoints 1 – 15 are currently active. Note: Bits
*	relating to endpoints that have not been configured will always return 0. Note also that all active interrupts are cleared when this
*	register is read.
**************************************************/
	WORD	IntrTxEn;				
/**************************************************
*	IntrTxE			address:06h, Reset value:16'hFFFF masked with the Tx endpoints implemented
*	IntrTxE is a 16-bit register that provides interrupt enable bits for the interrupts in IntrTx. Where a bit is set to 1, MC_NINT will
*	be asserted on the corresponding interrupt in the IntrTx register becoming set. Where a bit is set to 0, the interrupt in IntrTx is still set
*	but MC_NINT is not asserted. On reset, the bits corresponding to Endpoint 0 and the Tx endpoints included in the design are set to
*	1, while the remaining bits are set to 0. Note: Bits relating to endpoints that have not been configured will always return 0.
**************************************************/
	WORD	IntrRxEn;				
/**************************************************
*	IntrRxE			address:08h, Reset value:16'hFFFE masked with the Rx endpoints implemented
*	IntrRxE is a 16-bit register that provides interrupt enable bits for the interrupts in IntrRx. Where a bit is set to 1, MC_NINT will
*	be asserted on the corresponding interrupt in the IntrRx register becoming set. Where a bit is set to 0, the interrupt in IntrTx is still set
*	but MC_NINT is not asserted. On reset, the bits corresponding to the Rx endpoints included in the design are set to 1, while the
*	remaining bits are set to 0. Note: Bits relating to endpoints that have not been configured will always return 0.
**************************************************/
	BYTE	IntrUSB;				
/**************************************************
*	IntrUSB			address:0Ah, Reset value:8'h00
*	IntrUSB is an 8-bit read-only register that indicates which USB interrupts are currently active. 
*	All active interrupts will be cleared when this register is read.
**************************************************/
	BYTE	IntrUSBE;	
/**************************************************
*	IntrUSBE		address:0Bh, Reset value:8'h06
*	IntrUSBE is an 8-bit register that provides interrupt enable bits for each of the interrupts in IntrUSB.
**************************************************/			
	WORD	Frame;					
/**************************************************
*	Frame		address:0Ch, Reset value:16'h0000
*	Frame is a 16-bit register that holds the last received frame number.
**************************************************/	
	BYTE	Index;					
/**************************************************
*	Index		address:0Eh, Reset value:8'h00
*	Each Tx endpoint and each Rx endpoint have their own set of control/status registers located between 100h – 1FFh. In addition one
*	set of Tx control/status and one set of Rx control/status registers appear at 10h – 19h. Index is a 4-bit register that
*	determines which endpoint control/status registers are accessed.
**************************************************/	
	BYTE	TestMode;				
/**************************************************
*	TestMode	address:0Fh, Reset value:8'h00
*	Testmode is an 8-bit register that is primarily used to put the core into one of the four test modes for High-speed operation
*	described in the USB 2.0 specification – in response to a SET FEATURE: TESTMODE command. It is not used in norma
*	operation.
**************************************************/
}COMMON_USB_REG;


#define	Power_prw_IsoUpdate				(1 << 7)			
/**************************************************
*	When set by the CPU, the core will wait for an SOF token from the time TxPktRdy is the
*	before sending the packet. If an IN token is received before and SOF token, then a zero length
* data packet will be sent.
*	Note: Only valid in Peripheral Mode. alse, this bit only afects endpoints performing Isochronous
*				transfers.
**************************************************/	

#define	Power_prw_SoftConn				(1 << 6)				
/**************************************************
*	If Soft Connect/Disconnect feature is enabled, then the USB D+/D- lines are enabled when this bit
* is set by the CPU and tri-stated when this bit is cleared by the CPU. (See Section 5.1) 
*	Note: Only valid in Peripheral Mode.
**************************************************/	

#define	Power_prw_HSEnab				(1 << 5)		
#define	Power_hrw_HSEnab				(1 << 5)
/**************************************************
*	When set by the CPU, the core will negotiate for High-speed mode when the device is reset
* by the hub. If not set, the device will only operate in Full-speed mode.
**************************************************/	
		
#define	Power_pr_HSMode					(1 << 4)	
#define	Power_hr_HSMode					(1 << 4)		
/**************************************************
*	When set, this read-only bit indicates High-speed mode successfully negotiated during USB reset.
*	In Peripheral Mode, becomes valid when USB reset completes (as indicated by USB reset interrupt).
*	In Host Mode, becomes valid when Reset bit is cleared. Remains valid for the duration of the session.
*	Note: Allowance is made for Tiny -J signaling in determining the transfer speed to select.
**************************************************/	
	
#define	Power_pr_Reset					(1 << 3)	
#define	Power_hrw_Reset					(1 << 3)	
/**************************************************
*	This bit is set when Reset signaling is present on the bus. 
*	Note: This bit is Read/Write from the CPU in Host Mode but Read-Only in Peripheral Mode.
**************************************************/	

#define	Power_prw_Resume				(1 << 2)	
#define	Power_hrw_Resume				(1 << 2)
/**************************************************
*	Set by the CPU to generate Resume signaling when the function is in Suspend mode. The CPU should clear
*	this bit after 10 ms (a maximum of 15 ms) to end Resume signaling. In Host mode, this bit is also
*	automatically set when Resume signaling from the target is detected while the core is suspended.
**************************************************/	
			
#define	Power_pr_SuspendMode			(1 << 1)	
#define	Power_hs_SuspendMode			(1 << 1)
/**************************************************
*	In Host mode, this bit is set by the CPU to enter Suspend mode. In Peripheral mode, this bit is set on entry
*	into Suspend mode. It is cleared when the CPU reads the interrupt register, or sets the Resume bit above.
**************************************************/	
			
#define	Power_prw_EnSuspendMode			(1 << 0)	
#define	Power_hrw_EnSuspendMode			(1 << 0)		
/**************************************************
*	Set by the CPU to enable the SUSPENDM signal.
**************************************************/	
	



#define	IntUSB_VBusErr					(1 << 7)
/**************************************************
*	Set when VBus drops below the VBus Valid threshold during a session. Only valid when
*	core is ‘A’ device.
**************************************************/

#define	IntUSB_SessReq					(1 << 6)
/**************************************************
*	Set when Session Request signaling has been detected. Only valid when core is ‘A’ device.
**************************************************/

#define	IntUSB_DisCon					(1 << 5)
/**************************************************
*	Set in Host mode when a device disconnect is detected. Set in Peripheral mode when a session
*	ends. Valid at all transaction speeds.
**************************************************/

#define	IntUSB_Conn						(1 << 4)
/**************************************************
*	Set when a device connection is detected. Only valid in Host mode. Valid at all transaction speeds.
**************************************************/

#define	IntUSB_SOF						(1 << 3)
/**************************************************
*	Set when a new frame starts.
**************************************************/

#define	IntUSB_p_Reset					(1 << 2)
#define	IntUSB_h_Babble					(1 << 2)
/**************************************************
*	Set in Peripheral mode when Reset signaling is detected on the bus.
*	Set in Host mode when babble is detected. 
*	Note: Only active after first SOF has been sent.
**************************************************/

#define	IntUSB_Resume					(1 << 1)
/**************************************************
*	Set when Resume signaling is detected on the bus while the core is in Suspend mode.
**************************************************/

#define	IntUSB_Suspend					(1 << 0)
/**************************************************
*	Set when Suspend signaling is detected on the bus. Only valid in Peripheral mode.
**************************************************/