test_host.c

一个USB主机核的驱动程序

	if (!TestOTGCtrlSetupTransaction(GetStrDescriptorProduct, 8))
		return FALSE;
	if (!TestOTGCtrlInTransaction(val[5], &length, 0))
		return FALSE;
	if (!TestOTGCtrlOutTransaction(0, 0, 1))
		return FALSE;
#endif

	/* set configuration */
	if (!TestOTGCtrlSetupTransaction(SetConfig, 8))
		return FALSE;
	if (!TestOTGCtrlInTransaction(0, 0, 1))
		return FALSE;

#if !TEST_INTERRUPT_XFER_EN
	/* get max LUN */
	if (!TestOTGCtrlSetupTransaction(GetMaxLUN, 8))
		return FALSE;
	if (!TestOTGCtrlInTransaction(val[6], &length, 0))
		return FALSE;
	if (!TestOTGCtrlOutTransaction(0, 0, 1))
		return FALSE;
#endif
	return TRUE;

#endif

}

extern BOOL
TestOTGBulkOutTransaction(
	BYTE			endPointNum,
	BYTE			*dat,
	WORD			length
	)
{
	WORD		temp;
#if TEST_DMA_EN
	DWORD		temp1;
#endif

	/* set endpoint number */
	WriteOTGReg8(otg_CommonUSB_Index, endPointNum);

#if TEST_DMA_EN
	ApplyREQ();
	memcpy((BYTE XDATA *)0xB000, dat, (length + 3) / 4 * 4);
	ReleaseREQ();
	/* single packet Tx */
	ClrBitOTGReg16(otg_IndexedCSR_TxCSR, TxCSR_hrw_DMAReqEnab);
	/* config DMA address and length */
	WriteOTGReg32(otg_DMA_Addr, 0xB000);
	temp1 = ReadOTGReg32(otg_DMA_Addr);
	WriteOTGReg32(otg_DMA_Count, length);
	temp1 = ReadOTGReg32(otg_DMA_Count);
	WriteOTGReg32(otg_DMA_Ctrl, 0);
	SetBitOTGReg32(otg_DMA_Ctrl, (endPointNum << 4));
	SetBitOTGReg32(otg_DMA_Ctrl, (DMA_Ctrl_EnDMA | DMA_Ctrl_Direction | DMA_Ctrl_IntrEn));
	temp1 = ReadOTGReg32(otg_DMA_Ctrl);
	/* wait DMA load data */
	while(1)
	{
		temp1 = ReadOTGReg32(otg_DMA_Intr);
		if ((temp1 & DMA_Intr_Ch1) != 0)	
			break;
	}/* end while */
#else
	/* load data into FIFO */
	LoadFIFOData((BYTE *)&otg_EndpointFIFO[endPointNum], dat, length);
#endif

	/* send out token */
	SetBitOTGReg16(otg_IndexedCSR_TxCSR, TxCSR_hrs_TxPktRdy);	

	/* Wait EndPoint Tx interrupt */
	while(1)
	{
//		temp = ReadOTGReg16(otg_CommonUSB_IntrTx);
//		if ((temp & (0x0001 << endPointNum)) != 0)
//			break;
		temp = ReadOTGReg16(otg_IndexedCSR_TxCSR);
		if ((temp & TxCSR_hrs_TxPktRdy) == 0)
			break;
	}/* end while */

	/* check CSR response */
	if ((temp & TxCSR_hrc_RxStall) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_TxCSR, TxCSR_hrc_RxStall);		/* get STALL response */
		return FALSE;
	}
	else if ((temp & TxCSR_hrc_Error) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_TxCSR, TxCSR_hrc_Error);			/* get ERROR response */
		
		return FALSE;
	}
	else if ((temp & TxCSR_hrc_NAKTimeout_IncompTx) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_TxCSR, TxCSR_hrc_NAKTimeout_IncompTx);		/* get NAK timeoue response */
		return FALSE;
	}
	else
	{
		return TRUE;			/* no STALL, ERROR, NAKTimeout */
	}	
}


extern BOOL
TestOTGBulkOutTransactionDMA(
	BYTE			endPointNum,
	BYTE			*dat,
	WORD			length
	)
{
	WORD		maxPacketSize;
	WORD		temp;
	DWORD		temp1;

	/* set endpoint number */
	WriteOTGReg8(otg_CommonUSB_Index, endPointNum);

//	ApplyREQ();
//	memset(dat, 0, length);
//	ReleaseREQ();

	/* config MPRx */
	maxPacketSize = (ReadOTGReg16(otg_IndexedCSR_TxMaxP) & 0x07FF);
	ClrBitOTGReg16(otg_IndexedCSR_TxMaxP, 0xF800);
	if (maxPacketSize == 512)	
		SetBitOTGReg16(otg_IndexedCSR_TxMaxP, (0x0000 << 11));	
	else if (maxPacketSize == 64)
		SetBitOTGReg16(otg_IndexedCSR_TxMaxP, (0x0007 << 11));

	/* config DMA */
	SetBitOTGReg16(otg_CommonUSB_IntrTxEn, (0x0001 << endPointNum));	
	SetBitOTGReg16(otg_IndexedCSR_TxCSR, (TxCSR_hrw_AutoSet | TxCSR_hrw_DMAReqEnab | TxCSR_hrw_DMAReqMode)); //config TxCSR
//	WriteOTGReg32(&otg_RqPktCount[endPointNum], length / maxPacketSize);		
//	temp1 = ReadOTGReg32(&otg_RqPktCount[endPointNum]);
	
	WriteOTGReg32(otg_DMA_Addr, (WORD)dat);
	WriteOTGReg32(otg_DMA_Count, length);
	WriteOTGReg32(otg_DMA_Ctrl, 0);
	SetBitOTGReg32(otg_DMA_Ctrl, (endPointNum << 4));
	SetBitOTGReg32(otg_DMA_Ctrl, (DMA_Ctrl_EnDMA | DMA_Ctrl_Direction | DMA_Ctrl_Mode | DMA_Ctrl_IntrEn));

	/* send out token */
//	SetBitOTGReg16(otg_IndexedCSR_TxCSR, TxCSR_hrs_TxPktRdy);

	/* wait DMA unload data */
	while(1)
	{
		temp1 = ReadOTGReg32(otg_DMA_Intr);
		if ((temp1 & DMA_Intr_Ch1) != 0)	
			break;
	}/* end while */
	ClrBitOTGReg32(otg_DMA_Ctrl, (DMA_Ctrl_EnDMA | DMA_Ctrl_Direction | DMA_Ctrl_Mode | DMA_Ctrl_IntrEn));
	ClrBitOTGReg16(otg_IndexedCSR_TxCSR, (TxCSR_hrw_AutoSet | TxCSR_hrw_DMAReqEnab | TxCSR_hrw_DMAReqMode));

	/* check CSR response */
	temp = ReadOTGReg16(otg_IndexedCSR_TxCSR);
	if ((temp & TxCSR_hrc_RxStall) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_TxCSR, TxCSR_hrc_RxStall);		/* get STALL response */
		return FALSE;
	}
	else if ((temp & TxCSR_hrc_Error) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_TxCSR, TxCSR_hrc_Error);			/* get ERROR response */
		
		return FALSE;
	}
	else if ((temp & TxCSR_hrc_NAKTimeout_IncompTx) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_TxCSR, TxCSR_hrc_NAKTimeout_IncompTx);		/* get NAK timeoue response */
		return FALSE;
	}
	else
	{
		return TRUE;			/* no STALL, ERROR, NAKTimeout */
	}
}


extern BOOL
TestOTGBulkInTransaction(
	BYTE			endPointNum,
	BYTE			*dat,
	WORD			*length
	)
{
	WORD		temp;
#if TEST_DMA_EN
	DWORD		temp1;
#endif

	/* set endpoint number */
	WriteOTGReg8(otg_CommonUSB_Index, endPointNum);

	/* send in token */
	SetBitOTGReg16(otg_IndexedCSR_RxCSR, RxCSR_hrw_ReqPkt);

	/* Wait EndPoint Rx interrupt */
	while(1)
	{
//		temp = ReadOTGReg16(otg_CommonUSB_IntrRx);
//		if ((temp & (0x0001 << endPointNum)) != 0)
//			break;
		temp = ReadOTGReg16(otg_IndexedCSR_RxCSR);
		if ((temp & RxCSR_hrc_RxPktRdy) != 0)
			break;
	}/* end while */			

	/* check CSR response */
	if ((temp & RxCSR_hrc_RxStall) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_RxCSR, RxCSR_hrc_RxStall);		/* get STALL response */
		return FALSE;
	}
	else if ((temp & RxCSR_hrc_Error) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_RxCSR, RxCSR_hrc_Error);		/* get ERROR response */
		return FALSE;
	}
	else if ((temp & RxCSR_hrc_DataError_NAKTimeout) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_RxCSR, RxCSR_hrc_DataError_NAKTimeout);		/* get NAK timeoue response */
		return FALSE;
	}
	else
	{
		temp = ReadOTGReg16(otg_IndexedCSR_RxCount);
#if TEST_DMA_EN
		/* single packet Rx */
		ClrBitOTGReg16(otg_IndexedCSR_RxCSR, RxCSR_hrw_DMAReqEnab);
		/* config DMA address and length */
		WriteOTGReg32(otg_DMA_Addr, 0xB000);
		temp1 = ReadOTGReg32(otg_DMA_Addr);
		WriteOTGReg32(otg_DMA_Count, temp);
		temp1 = ReadOTGReg32(otg_DMA_Count);
		WriteOTGReg32(otg_DMA_Ctrl, 0);
		SetBitOTGReg32(otg_DMA_Ctrl, (endPointNum << 4));
		SetBitOTGReg32(otg_DMA_Ctrl, (DMA_Ctrl_EnDMA | DMA_Ctrl_IntrEn));
		temp1 = ReadOTGReg32(otg_DMA_Ctrl);
		/* wait DMA load data */
		while(1)
		{
			temp1 = ReadOTGReg32(otg_DMA_Intr);
			if ((temp1 & DMA_Intr_Ch1) != 0)	
				break;
		}/* end while */
		ApplyREQ();
		memcpy(dat, (BYTE XDATA *)0xB000, temp);
		ReleaseREQ();
#else
		UnloadFIFOData((BYTE *)&otg_EndpointFIFO[endPointNum], dat, temp);
#endif
		ClrBitOTGReg16(otg_IndexedCSR_RxCSR, RxCSR_hrc_RxPktRdy);
		*length = temp;
		return TRUE;			/* no STALL, ERROR, NAKTimeout */
	}/* end else */
}


extern BOOL
TestOTGBulkInTransactionDMA(
	BYTE			endPointNum,
	BYTE			*dat,
	WORD			length
	)
{
	WORD		temp;
	DWORD		temp1;
	WORD		maxPacketSize;

	/* set endpoint number */
	WriteOTGReg8(otg_CommonUSB_Index, endPointNum);

	ApplyREQ();
	memset(dat, 0x5A, length);
	ReleaseREQ();

	/* config MPRx */
	maxPacketSize = (ReadOTGReg16(otg_IndexedCSR_RxMaxP) & 0x07FF);
	ClrBitOTGReg16(otg_IndexedCSR_RxMaxP, 0xF800);
	if (maxPacketSize == 512)	
		SetBitOTGReg16(otg_IndexedCSR_RxMaxP, (0x0000 << 11));	
	else if (maxPacketSize == 64)
		SetBitOTGReg16(otg_IndexedCSR_RxMaxP, (0x0007 << 11));	

	/* config DMA */
	SetBitOTGReg16(otg_CommonUSB_IntrRxEn, (0x0001 << endPointNum));	//disable Rx interrupt
	SetBitOTGReg16(otg_IndexedCSR_RxCSR, (RxCSR_hrw_AutoClear | RxCSR_hrw_AutoReq | RxCSR_hrw_DMAReqEnab | RxCSR_hrw_DMAReqMode)); //config RXCSR
	WriteOTGReg32(&otg_RqPktCount[endPointNum], length / maxPacketSize);		
//	temp = ReadOTGReg32(&otg_RqPktCount[endPointNum]);
	
	WriteOTGReg32(otg_DMA_Addr, (WORD)dat);
	WriteOTGReg32(otg_DMA_Count, length);
	WriteOTGReg32(otg_DMA_Ctrl, 0);
	SetBitOTGReg32(otg_DMA_Ctrl, (endPointNum << 4));
	SetBitOTGReg32(otg_DMA_Ctrl, (DMA_Ctrl_EnDMA | DMA_Ctrl_Mode | DMA_Ctrl_IntrEn));
	
	/* send first in token */
	SetBitOTGReg16(otg_IndexedCSR_RxCSR, RxCSR_hrw_ReqPkt);