test_host.c

一个USB主机核的驱动程序

/****************************************************************
*                      MT View Silicon Tech. Inc.
*
*    Copyright 2007, MT View Silicon Tech. Inc., ShangHai, China
*                    All rights reserved.
*
*
* Filename:      	test_host.c
*
* Programmer:    	Grey
*
* Created: 	 		11/xx/2007
*
* Description: 		OTG host test code
*					
*              
*****************************************************************/


#include "test_host.h"

#define	TEST_HCD_EN		0
#define	TEST_INTERRUPT_XFER_EN		1


#define	BULK_IN_EPNUM			2
#define	BULK_OUT_EPNUM			1
#define	INTERRUPT_IN_EPNUM		3
#define	INTERRUPT_OUT_EPNUM		4

#if TEST_HCD_EN
#include "hcd.h"
#endif

extern BOOL
TestOTGHostInit(VOID)
{
	BYTE	DATA	temp;
	WORD	DATA	to;

	/* start a session */
	SetBitOTGReg8(otg_CtrlFIFO_DevCtl, DevCtl_rw_Session);		/* check the ID pin sensing and verify the core and PHY IDDIG input. */
	
	/* check device connect interrupt */
	to = 5000;
	while(to)
	{		
		/* read IntrUSB register */
		temp = ReadOTGReg8(otg_CommonUSB_IntrUSB);
		if ((temp & IntUSB_Conn) != 0)
			break;
	}
	if (to == 0)
		return FALSE;		/* no device connect */

	/* check host mode */
	temp = ReadOTGReg8(otg_CtrlFIFO_DevCtl);
	if ((temp & DevCtl_r_HostMode) == 0)
		return FALSE;		/* not host mode */

	/* reset USB bus */
	/* send reset signal with high-speed and suspend enable */
	SetBitOTGReg8(otg_CommonUSB_Power, Power_hrw_Reset);
	WaitMs(200);
	/* clear reset signal */
	ClrBitOTGReg8(otg_CommonUSB_Power, Power_hrw_Reset);
	
	/* check device speed */
	temp = ReadOTGReg8(otg_CtrlFIFO_DevCtl);
	if ((temp & DevCtl_r_LSDev) != 0)
	{
		temp = 1;		/* low-speed device connected */
	}
	else if ((temp & DevCtl_r_FSDev) != 0)
	{
		temp = ReadOTGReg8(otg_CommonUSB_Power);	
		if ((temp & Power_hr_HSMode) == 0)	
			temp = 2;		/* full-speed device connected */
		else
			temp = 3;		/* high-speed device connected */
	}
	else
	{
		return FALSE;
	}		

	/* after this SOF will send */
	to = 1;
	while(to)
	{
		temp = ReadOTGReg8(otg_CommonUSB_IntrUSB);
		if ((temp & IntUSB_SOF) == 0)
			break;
		to--;
		WaitMs(10);
	}
	if (to != 0)
		return FALSE;

	return TRUE;
}


extern BOOL
TestOTGCtrlSetupTransaction(
	BYTE			*dat,
	WORD			length
	)
{
	WORD	DATA	temp;

	/* set endpoint 0 */	
	WriteOTGReg8(otg_CommonUSB_Index, 0);

	/* load data into FIFO */
	LoadFIFOData((BYTE *)&otg_EndpointFIFO[0], dat, length);
	
	/* send setup packet */
	SetBitOTGReg16(otg_IndexedCSR_CSR0, (CSR0_hrw_SetupPkt | CSR0_hrs_TxPktRdy));		/* note: these two bit must be set together */
	
	/* Wait EndPoint 0 Tx interrupt */
	while(1)
	{
//		temp = ReadOTGReg16(otg_CommonUSB_IntrTx);
//		if ((temp & 0x0001) != 0)
//			break;
		temp = ReadOTGReg16(otg_IndexedCSR_CSR0);
		if ((temp & CSR0_hrs_TxPktRdy) == 0)
			break;
	}/* end while */

	/* check CSR0 response */
//	temp = ReadOTGReg16(otg_IndexedCSR_CSR0);
	if ((temp & CSR0_hrc_RxStall) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_RxStall);	/* get STALL response */
		return FALSE;
	}
	else if ((temp & CSR0_hrc_Error) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_Error);		/* get ERROR response */	
		return FALSE;
	}
	else if ((temp & CSR0_hrc_NAKTimeout) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_NAKTimeout);		/* get NAK timeoue response */
		return FALSE;
	}
	else
	{
		return TRUE;			/* no STALL, ERROR, NAKTimeout */
	}
}


extern BOOL
TestOTGCtrlInTransaction(
	BYTE			*dat,
	WORD			*length,
	BOOL			isStatusPhase
	)
{
	WORD	DATA	temp;

	/* set endpoint 0 */	
	WriteOTGReg8(otg_CommonUSB_Index, 0);

	if (isStatusPhase)
	{
		/* set setup and status bit */
		SetBitOTGReg16(otg_IndexedCSR_CSR0, (CSR0_hrw_StatusPkt | CSR0_hrw_ReqPkt));
		
		/* wait Endpoint 0 Rx interrupt */
		while(1)
		{
//			temp = ReadOTGReg16(otg_CommonUSB_IntrTx);
//			if ((temp & 0x0001) != 0)
//				break;
			temp = ReadOTGReg16(otg_IndexedCSR_CSR0);
			if ((temp & CSR0_hrc_RxPktRdy) != 0)
				break;
		}/* end while */

		/* check CSR0 response */
//		temp = ReadOTGReg16(otg_IndexedCSR_CSR0);
		if ((temp & CSR0_hrc_RxStall) != 0)
		{
			ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_RxStall);		/* get STALL response */
			return FALSE;
		}
		else if ((temp & CSR0_hrc_Error) != 0)
		{
			ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_Error);		/* get ERROR response */
			return FALSE;
		}
		else if ((temp & CSR0_hrc_NAKTimeout) != 0)
		{
			ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_NAKTimeout);		/* get NAK timeoue response */
			return FALSE;
		}
		else if ((temp & CSR0_hrc_RxPktRdy) != 0)
		{
			ClrBitOTGReg16(otg_IndexedCSR_CSR0, (CSR0_hrw_StatusPkt | CSR0_hrc_RxPktRdy));
			return TRUE;			/* no STALL, ERROR, NAKTimeout */
		}
	}
	else
	{
		/* set request packet, start IN phase */
		SetBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrw_ReqPkt);
	
		/* wait Endpoint 0 Rx interrupt */
		while(1)
		{
//			temp = ReadOTGReg16(otg_CommonUSB_IntrTx);
//			if ((temp & 0x0001) != 0)
//				break;
			temp = ReadOTGReg16(otg_IndexedCSR_CSR0);
			if ((temp & CSR0_hrc_RxPktRdy) != 0)
				break;
		}/* end while */
	
		/* check CSR0 register */
//		temp = ReadOTGReg16(otg_IndexedCSR_CSR0);
		if ((temp & CSR0_hrc_RxStall) != 0)
		{
			ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_RxStall);		/* get STALL response */
			return FALSE;
		}
		else if ((temp & CSR0_hrc_Error) != 0)
		{
			ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_Error);		/* get ERROR response */
			return FALSE;
		}
		else if ((temp & CSR0_hrc_NAKTimeout) != 0)
		{
			ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_NAKTimeout);		/* get NAK timeoue response */
			return FALSE;
		}
		else if ((temp & CSR0_hrc_RxPktRdy) != 0)					
		{
			temp = ReadOTGReg16(otg_IndexedCSR_Count0);
			UnloadFIFOData((BYTE *)&otg_EndpointFIFO[0], dat, temp);
			ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_RxPktRdy);
			*length = temp;
			return TRUE;			/* get RxPktRdy response, load data from FIFO */
		}
	}/* end else */
}

extern BOOL
TestOTGCtrlOutTransaction(
	BYTE			*dat,
	WORD			length,
	BOOL			isStatusPhase
	)
{
	WORD	DATA	temp;

	/* set endpoint 0 */	
	WriteOTGReg8(otg_CommonUSB_Index, 0);

	if (isStatusPhase)
	{
		/* set OUT and status bit */
		SetBitOTGReg16(otg_IndexedCSR_CSR0, (CSR0_hrw_StatusPkt | CSR0_hrs_TxPktRdy));
	}
	else
	{
		/* load data into endpoint0 FIFO */
		LoadFIFOData((BYTE *)&otg_EndpointFIFO[0], dat, length);
		/* set OUT bit */
		SetBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrs_TxPktRdy);
	}

	/* wait Endpoint 0 Rx interrupt */
	while(1)
	{
//		temp = ReadOTGReg16(otg_CommonUSB_IntrTx);
//		if ((temp & 0x0001) != 0)
//			break;
		temp = ReadOTGReg16(otg_IndexedCSR_CSR0);
		if ((temp & CSR0_hrs_TxPktRdy) == 0)
			break;
	}/* end while */

	/* check register CSR0 */
//	temp = ReadOTGReg16(otg_IndexedCSR_CSR0);
	if ((temp & CSR0_hrc_RxStall) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_RxStall);		/* get STALL response */
		return FALSE;
	}
	else if ((temp & CSR0_hrc_Error) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_Error);		/* get ERROR response */
		return FALSE;
	}
	else if ((temp & CSR0_hrc_NAKTimeout) != 0)
	{
		ClrBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_hrc_NAKTimeout);		/* get NAK timeoue response */
		return FALSE;
	}
	else
	{
		return TRUE;			/* no STALL, ERROR, NAKTimeout */