otg_hal.c

一个USB主机核的驱动程序

/****************************************************************
*                      MT View Silicon Tech. Inc.
*
*    Copyright 2007, MT View Silicon Tech. Inc., ShangHai, China
*                    All rights reserved.
*
*
* Filename:      	otg_hal.c
*
* Programmer:    	Grey
*
* Created: 	 			10/xx/2007
*
* Description: 		OTG hareware abstract layer
*					
*              
*****************************************************************/

#include "otg_hal.h"

/*---------------------------------OTG register access--------------------------*/
extern BYTE
ReadOTGReg8(
	BYTE		*reg
	)
{
	BYTE	DATA	retVal;
	
	EnterCritical();
	/* read register */
	retVal = *reg;				

	/* check OTG_STATUS_READ_OK signal, wait OTG_STATUS_READ_OK == 1 */
	while((*otg_op_status & OTG_STATUS_READ_OK) == 0);	

	/* check OTG_READ_REQ signal */
	if ((*otg_op_status & OTG_READ_REQ) != 0)		/* OTG_READ_REQ == 1 */
		retVal = *otg_rd_read_data;	
	ExitCritical();

	return retVal;
}


extern VOID
WriteOTGReg8(
	BYTE		*reg,
	BYTE		val
	)
{	
	EnterCritical();
	/* write register */
	*reg = val;						
		
	/* check OTG_WRITE_BUSY signal, wait OTG_WRITE_BUSY == 0 */
	while((*otg_op_status & OTG_WRITE_BUSY) != 0);	
	ExitCritical();
}



extern WORD
ReadOTGReg16(
	WORD		*reg
	)
{
	BYTE	XDATA	*p = (BYTE XDATA *)reg;
	WORD	DATA	retVal;
	
	((BYTE *)&retVal)[0] = ReadOTGReg8(&p[1]);
	((BYTE *)&retVal)[1] = ReadOTGReg8(&p[0]);
	
	return retVal;
}

extern VOID
WriteOTGReg16(
	WORD		*reg,
	WORD		val
	)
{
	BYTE	XDATA 	*p = (BYTE XDATA *)reg;
	
	WriteOTGReg8(&p[1], ((BYTE *)&val)[0]);
	WriteOTGReg8(&p[0], ((BYTE *)&val)[1]);
}

extern DWORD
ReadOTGReg32(
	DWORD		*reg
	)
{
	BYTE	XDATA	*p = (BYTE XDATA *)reg;
	DWORD	DATA	retVal;
	
	((BYTE *)&retVal)[0] = ReadOTGReg8(&p[3]);
	((BYTE *)&retVal)[1] = ReadOTGReg8(&p[2]);
	((BYTE *)&retVal)[2] = ReadOTGReg8(&p[1]);
	((BYTE *)&retVal)[3] = ReadOTGReg8(&p[0]);
	
	return retVal;
}

extern VOID
WriteOTGReg32(
	DWORD		*reg,
	DWORD		val
	)
{
	BYTE	XDATA 	*p = (BYTE XDATA *)reg;

	WriteOTGReg8(&p[3], ((BYTE *)&val)[0]);
	WriteOTGReg8(&p[2], ((BYTE *)&val)[1]);
	WriteOTGReg8(&p[1], ((BYTE *)&val)[2]);
	WriteOTGReg8(&p[0], ((BYTE *)&val)[3]);
}


extern VOID
SetBitOTGReg8(
	BYTE 		*reg,
	BYTE		mask
	)
{
	BYTE	DATA	temp;
	
	temp = ReadOTGReg8(reg);	
	temp |= mask;	
	WriteOTGReg8(reg, temp);		
}

extern VOID
SetBitOTGReg16(
	WORD 		*reg,
	WORD		mask
	)
{
	WORD	DATA	temp;
	
	temp = ReadOTGReg16(reg);	
	temp |= mask;	
	WriteOTGReg16(reg, temp);	
}

extern VOID
SetBitOTGReg32(
	DWORD 		*reg,
	DWORD		mask
	)
{
	DWORD	DATA	temp;
	
	temp = ReadOTGReg32(reg);	
	temp |= mask;	
	WriteOTGReg32(reg, temp);
}


extern VOID
ClrBitOTGReg8(
	BYTE		*reg,
	BYTE		mask
	)
{
	BYTE	DATA	temp;
	
	temp = ReadOTGReg8(reg);	
	temp &= ~mask;	
	WriteOTGReg8(reg, temp);	
}

extern VOID
ClrBitOTGReg16(
	WORD		*reg,
	WORD		mask
	)
{
	WORD	DATA	temp;
	
	temp = ReadOTGReg16(reg);	
	temp &= ~mask;	
	WriteOTGReg16(reg, temp);
}

extern VOID
ClrBitOTGReg32(
	DWORD		*reg,
	DWORD		mask
	)
{
	DWORD	DATA	temp;
	
	temp = ReadOTGReg32(reg);	
	temp &= ~mask;	
	WriteOTGReg32(reg, temp);
}


extern VOID
ToggleBitOTGReg8(
	BYTE		*reg,
	BYTE		mask
	)
{
	BYTE	DATA	temp;
	
	temp = ReadOTGReg8(reg);	
	temp ^= mask;	
	WriteOTGReg8(reg, temp);
}

extern VOID
ToggleBitOTGReg16(
	WORD		*reg,
	WORD		mask
	)
{
	WORD	DATA	temp;
	
	temp = ReadOTGReg16(reg);	
	temp ^= mask;	
	WriteOTGReg16(reg, temp);
}
/*--------------------------------------------------------------------------*/

/*------------------------------Data FIFO access----------------------------*/
extern VOID
LoadFIFOData(
	BYTE			*fifo,
	BYTE			*dat,
	WORD			length
	)
{
	/* load data from data buffer into FIFO */
	while(length)
	{
		WriteOTGReg8(fifo, *dat);		/* write fifo data */
		dat++;
		length--;
	}/* end while */
}

extern VOID
UnloadFIFOData(
	BYTE			*fifo,
	BYTE			*dat,
	WORD			length
	)
{
	/* unload data from FIFO into data buffer */
	while(length)
	{
		*dat = ReadOTGReg8(fifo);					/* read fifo data from data address 0 */
		dat++;
		length--;
	}/* end while */
}
/*----------------------------------------------------------------------------*/

/*---------------------------------OTG mode config------------------------------*/
/*
 *	close high-speed mode
 */
extern VOID
ForceOTGFullSpeed(VOID)
{
	ClrBitOTGReg8(otg_CommonUSB_Power, Power_hrw_HSEnab);
}


/*
 *	force OTG IDDIG = 0, set A-device
 */
extern VOID
ForceOTGADevMode(VOID)
{
	*utmi_src_sel &= ~OTG_UTMI_IDDIG;
	*utmi_src_sel_en |= OTG_UTMI_IDDIG;
}


/*
 *	force OTG IDDIG = 1, set B-device
 */
extern VOID
ForceOTGBDevMode(VOID)
{
	*utmi_src_sel |= OTG_UTMI_IDDIG;
	*utmi_src_sel_en |= OTG_UTMI_IDDIG;
}


/*
 *	force OTG VBusValid = 1, do not care the VBusValid from PHY
 */
extern VOID
ForceOTGVBusValid(VOID)
{
	*utmi_src_sel |= OTG_UTMI_VBUSVALID;
	*utmi_src_sel_en |= OTG_UTMI_VBUSVALID;
}
/*-------------------------------------------------------------------------------*/



/*---------------------------------for debug-------------------------------*/
extern VOID
ApplyREQ(VOID)
{
	*mem_access &= ~mem_access_Req;
	while((*mem_access & mem_access_Ack) != 0);
}

extern VOID
ReleaseREQ(VOID)
{
	*mem_access |= mem_access_Req;
}

/*
 *	Open OTG core, allocate register and init the core
 */
extern VOID
OpenOTG(VOID)
{
	/* set high speed enable, enable suspend mode */
//	SetBitOTGReg8(otg_CommonUSB_Power, (Power_hrw_HSEnab | Power_hrw_EnSuspendMode));		/* set this bit, PLL will be closed when suspend */
	SetBitOTGReg8(otg_CommonUSB_Power, Power_hrw_HSEnab);


	/* enable all usb interrupt */
	WriteOTGReg8(otg_CommonUSB_IntrUSBE, 0xFF);
}
/*--------------------------------------------------------------------------*/