test_otg_testmode.c

一个USB主机核的驱动程序

/****************************************************************
*                      MT View Silicon Tech. Inc.
*
*    Copyright 2007, MT View Silicon Tech. Inc., ShangHai, China
*                    All rights reserved.
*
*
* Filename:      	test_otg_testmode.c
*
* Programmer:    	Grey
*
* Created: 	 		11/xx/2007
*
* Description: 		OTG TestMode test code
*					
*              
*****************************************************************/


#include "test_otg_testmode.h"


extern BOOL
TestOTGPHY(VOID)
{
	BYTE	DATA	temp;
//	DWORD		temp;
	

	/* force host mode */
	SetBitOTGReg8(otg_CommonUSB_TestMode, TestMode_rw_ForceHost);
	temp = ReadOTGReg8(otg_CommonUSB_TestMode);


	/* test J */
	SetBitOTGReg8(otg_CommonUSB_TestMode, TestMode_rw_J);
	temp = ReadOTGReg8(otg_CommonUSB_TestMode);
	ClrBitOTGReg8(otg_CommonUSB_TestMode, TestMode_rw_J);
	temp = ReadOTGReg8(otg_CommonUSB_TestMode);

	/* test K */
	SetBitOTGReg8(otg_CommonUSB_TestMode, TestMode_rw_K);
	temp = ReadOTGReg8(otg_CommonUSB_TestMode);
	ClrBitOTGReg8(otg_CommonUSB_TestMode, TestMode_rw_K);
	temp = ReadOTGReg8(otg_CommonUSB_TestMode);


	return TRUE;
}



extern BOOL
TestOTGFIFOAccess(VOID)
{
	BYTE	DATA	i;
	BYTE	XDATA	*p = (BYTE *)&otg_EndpointFIFO[0];
	BYTE	DATA	temp;
	WORD	DATA	temp1;
	BYTE	XDATA	val[64];

	/* select endpoint 0 */
	WriteOTGReg8(otg_CommonUSB_Index, 0);

	/* load FIFO data */
	for (i = 0; i < 64; ++i)
		WriteOTGReg8(p, i);

	/* set TxPktRdy signal */
	SetBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_prs_TxPktRdy);
	
	/* set TestMode FIFOAccess signal */
	SetBitOTGReg8(otg_CommonUSB_TestMode, TestMode_rw_FIFOAccess);

	/* check endpoint 0 Tx interrupt */
	do
	{
		temp = ReadOTGReg16(otg_CommonUSB_IntrTx);
	}
	while(temp == 0);
	if ((temp & 0x0001) == 0)
		return FALSE;
	
	/* check RxPktRdy signal */
	temp1 = ReadOTGReg16(otg_IndexedCSR_CSR0);
	if ((temp1 & CSR0_pr_RxPktRdy) == 0 || (temp1 & CSR0_prs_TxPktRdy) != 0)
		return FALSE;

	/* get endpoint 0 Rx count */
	temp1 = ReadOTGReg16(otg_IndexedCSR_Count0);

	/* unload data from FIFO */
	for (i = 0; i < temp1; ++i)
		val[i] = ReadOTGReg8(p);			/* no data received */

	/* set ServicedRxPktRdy signal */
	SetBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_ps_ServicedRxPktRdy);
	
	return TRUE;
}



extern BOOL
TestOTGPacket(VOID)
{
	static 	BYTE	CODE	testData[] = {0, 0, 0, 0, 0, 0, 0, 0,
									0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
									0xAA, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
									0xEE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
									0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xBF, 0xDf,
									0xEF, 0xF7, 0xFB, 0xFD, 0xFC, 0x7E, 0xBF, 0xDF,
									0xEF, 0xF7, 0xFB, 0xFD, 0x7E,};
	
	/* select endpoint 0 */
	WriteOTGReg8(otg_CommonUSB_Index, 0);

	/* force host mode */
//	SetBitOTGReg8(otg_CommonUSB_TestMode, TestMode_rw_ForceHost);
	/* set high speed mode */
//	ClrBitOTGReg8(otg_CommonUSB_TestMode, TestMode_rw_ForceFS);
//	SetBitOTGReg8(otg_CommonUSB_TestMode, TestMode_rw_ForceHS);

	/* host req */
	SetBitOTGReg8(otg_CtrlFIFO_DevCtl, DevCtl_rw_HostReq);
	if ((ReadOTGReg8(otg_CtrlFIFO_DevCtl) & DevCtl_r_HostMode) == 0)
		return FALSE;

	/* start session */
	SetBitOTGReg8(otg_CtrlFIFO_DevCtl, DevCtl_rw_Session);

	/* load data into endpoint fifo */
	LoadFIFOData((BYTE *)&otg_EndpointFIFO[0], testData, sizeof(testData));

	/* set TestMode TestMode_rw_Packet signal */
	SetBitOTGReg8(otg_CommonUSB_TestMode, TestMode_rw_Packet);

	/* set TxPktRdy signal */
	SetBitOTGReg16(otg_IndexedCSR_CSR0, CSR0_prs_TxPktRdy);

	return TRUE;
}