chipcon_demo.sym

mc68hc908jb8的usb代码

__S0 2100 0
__S1 190 0
_WakeUpCC1000ToRX F2D 0 CODE
__H__Z16978RS_ 190 0
__L__Z16978RS_ 190 0
?a_halSpiReadBurstReg 4E 0 BANK0
_flag 33 0 BANK0
_main FD7 0 CODE
_exit 9E 0 CODE
start 9E 0 CODE
?a_SPI_read 51 0 BANK0
__Hintsave_0 80 0 COMBANK
__Lintsave_0 7F 0 COMBANK
_ResetCC1000 DCE 0 CODE
_SetupCC1000 F7B 0 CODE
__Hintcode 95 0 CODE
__Lintcode F 0 CODE
_PreambleEnd 26 0 BANK0
__Hintsave_1 190 0
__Lintsave_1 190 0
_State 2C 0 BANK0
_delay 2F 0 BANK0
?a_POWER_UP_RESET_CCxxx0 45 0 BANK0
?a_halSpiReadReg 4C 0 BANK0
__Hintsave_2 190 0
__Lintsave_2 190 0
__Hintsave 190 0
__Lintsave 190 0
_SPI_write 2EE 0 CODE
_TXBufferIndex1 2E 0 BANK0
_Statusflag 2D 0 BANK0
__Hintsave_3 190 0
__Lintsave_3 190 0
_dpybuffer 65 0 BANK0
_Dly1mS 38E 0 CODE
__Hcode 190 0
__Lcode 190 0
__Hstrings E2 0 STRING
__Lstrings E2 0 STRING
__Htemp 79 0 BANK0
__Ltemp 77 0 BANK0
__Hinit B4 0 CODE
__Linit 9E 0 CODE
_CheckState FB3 0 CODE
powerup 0 0 CODE
__Htext 190 0
__Ltext 190 0
__Hpowerup 4 0 CODE
__Lpowerup 0 0 CODE
_POWER_UP_RESET_CCxxx0 70E 0 CODE
__Hvectors FE 0 CODE
__Lvectors FE 0 CODE
_TestingCC1000 499 0 CODE
_BytesToSend 56 0 BANK0
__Hclrtext CC 0 CODE
__Lclrtext B8 0 CODE
?a_ResetCC1000 43 0 BANK0
int_restore 99 0 CODE
?_halRfReceivePacket 47 0 BANK0
used_code_ptr 1 0
string_table CC 0 ENTRY
_halRfSendPacket 3A0 0 CODE
?_Dly1mS 4C 0 BANK0
?_SetupCC1000RX 44 0 BANK0
_Current_Mode 22 0 BANK0
_BitCounter 20 0 BANK0
_Keyflag 24 0 BANK0
__Hidloc 2000 0 IDLOC
__Lidloc 2000 0 IDLOC
_KeyScan 438 0 CODE
__Hpstrings E2 0 CODE
__Lpstrings E2 0 CODE
_PreambleError 27 0 BANK0
__Hend_init B8 0 CODE
__Lend_init B4 0 CODE
int_func F 0 CODE
_halSpiReadReg 30F 0 CODE
__Hnvram 79 0 BANK0
__Lnvram 79 0 BANK0
_Old_key 54 0 BANK0
code_ptr 7C 0 BANK0
__Hfloat_text0 E2 0 CODE
?a_CalibrateCC1000 49 0 BANK0
__Lfloat_text0 E2 0 CODE
?_WakeUpCC1000ToRX 43 0 BANK0
?_WakeUpCC1000ToTX 43 0 BANK0
?a_RxCCxx00 45 0 BANK0
?a_TxCCxx00 45 0 BANK0
__Hcode_ptr 7E 0 BANK0
__Lcode_ptr 7C 0 BANK0
_RxCCxx00 547 0 CODE
_TxCCxx00 464 0 CODE
?_WriteToCC1000Register 4B 0 BANK0
__Hinit23 B4 0 CODE
__Linit23 B4 0 CODE
_paTable_CC1100 A0 0 BANK1
?a_SPI_write 51 0 BANK0
_RXBufferWriteIndex 2A 0 BANK0
_ReadFromCC1000Register D90 0 CODE
?a_ConfigureCC1000 43 0 BANK0
_halSpiReadBurstReg 33C 0 CODE
_TestingCCxx00 75E 0 CODE
__Hfloat_text1 E2 0 CODE
__Lfloat_text1 E2 0 CODE
__Brbit_0 20 FFFFFF20 BANK0
__Hrbit_0 100 FFFFFF20 BANK0
__Lrbit_0 100 FFFFFF20 BANK0
__Brbit_1 A0 FFFFFBA0 BANK1
__Hrbss_0 54 0 BANK0
__Hrbit_1 500 FFFFFBA0 BANK1
__Lrbss_0 20 0 BANK0
__Lrbit_1 500 FFFFFBA0 BANK1
__Brbit_2 110 FFFFF890 BANK2
__Hrbss_1 A0 0 BANK1
__Hrbit_2 880 FFFFF890 BANK2
__Lrbss_1 A0 0 BANK1
__Lrbit_2 880 FFFFF890 BANK2
?_SetupCC1000TX 44 0 BANK0
__Brbit_3 190 FFFFF510 BANK3
__Hrbss_2 110 0 BANK2
__Hrbit_3 C80 FFFFF510 BANK3
__Lrbss_2 110 0 BANK2
__Lrbit_3 C80 FFFFF510 BANK3
__Hrbss_3 190 0 BANK3
__Lrbss_3 190 0 BANK3
__Hintentry F 0 CODE
__Lintentry 4 0 CODE
intlevel0 4 0 CODE
intlevel1 4 0 CODE
_halSpiStrobe 378 0 CODE
_PA_POWER 55 0 BANK0
_PreambleCount 25 0 BANK0
_halRfWriteRfSettings_CC1100 643 0 CODE
?a_spiGetRxTxStatus 43 0 BANK0
?_halRfSendPacket 46 0 BANK0
_rxBuffer_CCxx00 37 0 BANK0
_txBuffer_CCxx00 58 0 BANK0
_halRfWriteRfSettings_CC2500 572 0 CODE
?a_SetupCC1000RX 45 0 BANK0
__Hfloat_text2 E2 0 CODE
__Lfloat_text2 E2 0 CODE
string_indir CF 0 ENTRY
_ResetFreqSynth DDA 0 CODE
?a_ReadFromCC1000Register 4B 0 BANK0
?a_TestingCCxx00 43 0 BANK0
_SPI_read 2D7 0 CODE
_ShiftReg 2B 0 BANK0
_ByteCounter 21 0 BANK0
_paTable_CC2500 A8 0 BANK1
copy_data BF 0 CODE
__Hconfig 2008 0 CONFIG
__Lconfig 2007 0 CONFIG
?a_halSpiWriteBurstReg 4A 0 BANK0
_halRfReceivePacket 3D5 0 CODE
__Hfloat_text3 E2 0 CODE
__Lfloat_text3 E2 0 CODE
clear_ram BB 0 CODE
_RXBuffer 30 0 BANK0
_TXBuffer 6F 0 BANK0
__Hintret 9E 0 CODE
__Lintret 95 0 CODE
__Hstruct 7F 0 BANK0
__Lstruct 7F 0 BANK0
clear_bank0 9E 0 CODE
_BytesToReceive 57 0 BANK0
_Current_key 23 0 BANK0
_SetupCCxx00 736 0 CODE
int_entry 4 0 CODE
?a_halSpiStrobe 4C 0 BANK0
used_btemp0 1 0
save_btemp0 D 0 CODE
_SetupCC1000RX E86 0 CODE
__Hfloat_text4 E2 0 CODE
__Lfloat_text4 E2 0 CODE
?_halSpiWriteBurstReg 48 0 BANK0
used_btemp1 1 0
?a_halRfSendPacket 47 0 BANK0
?a_halSpiReadStatus 4C 0 BANK0
_CalibrateCC1000 E3F 0 CODE
__Hcommon_ram 190 0
__Lcommon_ram 190 0
_WakeUpCC1000ToTX F52 0 CODE
?_halSpiWriteReg 46 0 BANK0
?a_TestingCC1000 43 0 BANK0
_ConfigureCC1000 E18 0 CODE
_SetupCC1000TX ED2 0 CODE
?_halSpiReadBurstReg 4C 0 BANK0
?a_ResetFreqSynth 49 0 BANK0
__Hidata_0 800 0 CODE
__Lidata_0 7DD 0 CODE
__Hrdata_0 77 0 BANK0
__Lrdata_0 54 0 BANK0
__Hidata_1 7DD 0 CODE
__Lidata_1 7CD 0 CODE
__Heeprom_data 2100 0 EEDATA
__Leeprom_data 2100 0 EEDATA
__Hrdata_1 B0 0 BANK1
__Lrdata_1 A0 0 BANK1
_halSpiReadStatus 31E 0 CODE
_WriteToCC1000Register DE6 0 CODE
__Hidata_2 E2 0 CODE
__Lidata_2 E2 0 CODE
__Hrdata_2 110 0 BANK2
__Lrdata_2 110 0 BANK2
__Hidata_3 E2 0 CODE
__Lidata_3 E2 0 CODE
__Hrdata_3 190 0 BANK3
__Lrdata_3 190 0 BANK3
__Hnvram_1 B0 0 BANK1
__Lnvram_1 B0 0 BANK1
__Bnvbit_0 79 FFFFFCB1 BANK0
__Hnvbit_0 3C8 FFFFFCB1 BANK0
__Lnvbit_0 3C8 FFFFFCB1 BANK0
__Hnvram_2 110 0 BANK2
__Lnvram_2 110 0 BANK2
__Bnvbit_1 B0 FFFFFB30 BANK1
__Hnvbit_1 580 FFFFFB30 BANK1
__Lnvbit_1 580 FFFFFB30 BANK1
__Hnvram_3 190 0 BANK3
__Lnvram_3 190 0 BANK3
?a_SetupCC1000TX 45 0 BANK0
__Bnvbit_2 110 FFFFF890 BANK2
__Hnvbit_2 880 FFFFF890 BANK2
__Lnvbit_2 880 FFFFF890 BANK2
__Bnvbit_3 190 FFFFF510 BANK3
__Hnvbit_3 C80 FFFFF510 BANK3
__Lnvbit_3 C80 FFFFF510 BANK3
copy_bank0 A2 0 CODE
copy_bank1 AB 0 CODE
?a_halRfReceivePacket 48 0 BANK0
__Hstringtable E2 0 ENTRY
__Lstringtable CC 0 ENTRY
_halSpiWriteReg 32E 0 CODE
?a_halSpiWriteReg 47 0 BANK0
?a_WakeUpCC1000ToRX 44 0 BANK0
?a_WakeUpCC1000ToTX 44 0 BANK0
_RXBufferReadIndex 29 0 BANK0
_InitPIC16F877A 419 0 CODE
_SetupCC1000PD F25 0 CODE
?a_WriteToCC1000Register 4C 0 BANK0
_spiGetRxTxStatus 383 0 CODE
_PreambleLength 28 0 BANK0
_Configuration E3 0 CONST
_halSpiWriteBurstReg 357 0 CODE
%segments
powerup 0 7 CODE
intentry 8 1C3 CODE
rbit_0 100 156 BANK0
idata_0 FBA FFF CODE
rbit_1 500 50F BANK1
idata_1 F9A FB9 CODE
temp 77 78 COMBANK
config 400E 400F CONFIG
nvram 79 7E BANK0
text33 A8E F99 CODE
text2 5AE A8D CODE
text17 1B20 1FFF CODE
const1 1C4 1FB CONST
intsave_0 7F 7F COMBANK
%locals
E:\mywork\chipcon_demo\cc1100+cc2500+cc1000\main.obj
_isr F 0 CODE
pc 2
fsr 4
btemp 77 0 BANK0
saved_w 7F 0 COMBANK
saved_fsr 7A 0 BANK0
saved_pclath 7B 0 BANK0
pclath A
saved_status 79 0 BANK0
status 3
l_loop_dly 391 0 CODE
E:\mywork\chipcon_demo\cc1100+cc2500+cc1000\CCxxx0LIB.C
80 2D7 0 CODE
82 2D7 0 CODE
84 2D9 0 CODE
85 2DB 0 CODE
86 2DC 0 CODE
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88 2E1 0 CODE
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92 2EC 0 CODE
93 2ED 0 CODE
48 2EE 0 CODE
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53 2F1 0 CODE
51 2F2 0 CODE
54 2F4 0 CODE
55 2F5 0 CODE
59 2F6 0 CODE
61 2F7 0 CODE
62 2FC 0 CODE
63 2FD 0 CODE
64 2FF 0 CODE
65 301 0 CODE
66 304 0 CODE
68 306 0 CODE
50 307 0 CODE
70 30A 0 CODE
50 30B 0 CODE
72 30D 0 CODE
73 30E 0 CODE
111 30F 0 CODE
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114 312 0 CODE
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119 31A 0 CODE
120 31B 0 CODE
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149 32A 0 CODE
150 32B 0 CODE
151 32C 0 CODE
153 32D 0 CODE
169 32E 0 CODE
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176 339 0 CODE
177 33A 0 CODE
179 33B 0 CODE
198 33C 0 CODE
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207 34B 0 CODE
208 34D 0 CODE
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240 36B 0 CODE
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262 378 0 CODE
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567 383 0 CODE
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571 387 0 CODE
572 38A 0 CODE
573 38B 0 CODE
574 38C 0 CODE
576 38D 0 CODE
28 38E 0 CODE
31 38F 0 CODE
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28 394 0 CODE
285 3A0 0 CODE
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288 3AA 0 CODE
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306 3BE 0 CODE
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313 3CA 0 CODE
314 3CE 0 CODE
316 3D0 0 CODE
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343 3D5 0 CODE
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347 3DD 0 CODE
349 3E0 0 CODE
350 3EB 0 CODE
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378 418 0 CODE
E:\mywork\chipcon_demo\cc1100+cc2500+cc1000\main.c
171 419 0 CODE
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