8.hier_info

实现对ad的控制并用7279芯片进行显示

|8
clk7279 <= hd7279:inst.CLK7279
clk => hd7279:inst.CLK
clk => ADC0809:inst3.clk
RST_N => hd7279:inst.RST_N
RST_N => ADC0809:inst3.RST_N
key7279 => hd7279:inst.key7279
dat7279 <= hd7279:inst.DAT7279
eoc => ADC0809:inst3.eoc
d[0] => ADC0809:inst3.d[0]
d[1] => ADC0809:inst3.d[1]
d[2] => ADC0809:inst3.d[2]
d[3] => ADC0809:inst3.d[3]
d[4] => ADC0809:inst3.d[4]
d[5] => ADC0809:inst3.d[5]
d[6] => ADC0809:inst3.d[6]
d[7] => ADC0809:inst3.d[7]
clk2 <= hd7279:inst.clk2
cs7279 <= hd7279:inst.CS7279
start <= ADC0809:inst3.start
ale <= ADC0809:inst3.ale
en <= ADC0809:inst3.en
clk1 <= ADC0809:inst3.clk1
channel[0] <= hd7279:inst.channel[0]
channel[1] <= hd7279:inst.channel[1]
channel[2] <= hd7279:inst.channel[2]
q[0] <= ADC0809:inst3.q[0]
q[1] <= ADC0809:inst3.q[1]
q[2] <= ADC0809:inst3.q[2]
q[3] <= ADC0809:inst3.q[3]
q[4] <= ADC0809:inst3.q[4]
q[5] <= ADC0809:inst3.q[5]
q[6] <= ADC0809:inst3.q[6]
q[7] <= ADC0809:inst3.q[7]


|8|hd7279:inst
CLK => count[30].CLK
CLK => count[29].CLK
CLK => count[28].CLK
CLK => count[27].CLK
CLK => count[26].CLK
CLK => count[25].CLK
CLK => count[24].CLK
CLK => count[23].CLK
CLK => count[22].CLK
CLK => count[21].CLK
CLK => count[20].CLK
CLK => count[19].CLK
CLK => count[18].CLK
CLK => count[17].CLK
CLK => count[16].CLK
CLK => count[15].CLK
CLK => count[14].CLK
CLK => count[13].CLK
CLK => count[12].CLK
CLK => count[11].CLK
CLK => count[10].CLK
CLK => count[9].CLK
CLK => count[8].CLK
CLK => count[7].CLK
CLK => count[6].CLK
CLK => count[5].CLK
CLK => count[4].CLK
CLK => count[3].CLK
CLK => count[2].CLK
CLK => count[1].CLK
CLK => count[0].CLK
CLK => t.CLK
CLK => count[31].CLK
RST_N => CS7279~reg0.PRESET
RST_N => CLK7279~reg0.ACLR
RST_N => DAT7279~reg0.ACLR
RST_N => p2~0.ACLR
RST_N => delay_cnt[1].ENA
RST_N => delay_cnt[0].ENA
RST_N => scmd_cnt[2].ENA
RST_N => scmd_cnt[1].ENA
RST_N => scmd_cnt[0].ENA
RST_N => sdata_cnt[2].ENA
RST_N => sdata_cnt[1].ENA
RST_N => sdata_cnt[0].ENA
RST_N => state~16.IN1
D_BUS1[0] => data_tmp~7.DATAB
D_BUS1[1] => data_tmp~6.DATAB
D_BUS1[2] => data_tmp~5.DATAB
D_BUS1[3] => data_tmp~4.DATAB
D_BUS1[4] => data_tmp~3.DATAB
D_BUS1[5] => data_tmp~2.DATAB
D_BUS1[6] => data_tmp~1.DATAB
D_BUS2[0] => data_tmp~15.DATAB
D_BUS2[1] => data_tmp~14.DATAB
D_BUS2[2] => data_tmp~13.DATAB
D_BUS2[3] => data_tmp~12.DATAB
D_BUS2[4] => data_tmp~11.DATAB
D_BUS2[5] => data_tmp~10.DATAB
D_BUS2[6] => data_tmp~9.DATAB
D_BUS3[0] => data_tmp~23.DATAB
D_BUS3[1] => data_tmp~22.DATAB
D_BUS3[2] => data_tmp~21.DATAB
D_BUS3[3] => data_tmp~20.DATAB
D_BUS3[4] => data_tmp~19.DATAB
D_BUS3[5] => data_tmp~18.DATAB
D_BUS3[6] => data_tmp~17.DATAB
key7279 => cmd_tmp~0.OUTPUTSELECT
key7279 => cmd_tmp~1.OUTPUTSELECT
key7279 => cmd_tmp~2.OUTPUTSELECT
key7279 => Select~22.IN4
key7279 => cmd_tmp[7].DATAIN
abc[0] => ~NO_FANOUT~
abc[1] => ~NO_FANOUT~
abc[2] => ~NO_FANOUT~
D_BUS4[0] => data_tmp~31.DATAB
D_BUS4[1] => data_tmp~30.DATAB
D_BUS4[2] => data_tmp~29.DATAB
D_BUS4[3] => data_tmp~28.DATAB
D_BUS4[4] => data_tmp~27.DATAB
D_BUS4[5] => data_tmp~26.DATAB
D_BUS4[6] => data_tmp~25.DATAB
CLK7279 <= CLK7279~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk2 <= t.DB_MAX_OUTPUT_PORT_TYPE
CS7279 <= CS7279~reg0.DB_MAX_OUTPUT_PORT_TYPE
DAT7279 <= p2~1
channel[0] <= key_7279[0].DB_MAX_OUTPUT_PORT_TYPE
channel[1] <= key_7279[1].DB_MAX_OUTPUT_PORT_TYPE
channel[2] <= key_7279[2].DB_MAX_OUTPUT_PORT_TYPE


|8|ADC0809:inst3
RST_N => current_state~1.IN1
dataout1[0] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
dataout1[1] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
dataout1[2] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
dataout1[3] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
dataout1[4] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
dataout1[5] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
dataout1[6] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
dataout2[0] <= Mux~13.DB_MAX_OUTPUT_PORT_TYPE
dataout2[1] <= Mux~12.DB_MAX_OUTPUT_PORT_TYPE
dataout2[2] <= Mux~11.DB_MAX_OUTPUT_PORT_TYPE
dataout2[3] <= Mux~10.DB_MAX_OUTPUT_PORT_TYPE
dataout2[4] <= Mux~9.DB_MAX_OUTPUT_PORT_TYPE
dataout2[5] <= Mux~8.DB_MAX_OUTPUT_PORT_TYPE
dataout2[6] <= Mux~7.DB_MAX_OUTPUT_PORT_TYPE
dataout3[0] <= Mux~20.DB_MAX_OUTPUT_PORT_TYPE
dataout3[1] <= Mux~19.DB_MAX_OUTPUT_PORT_TYPE
dataout3[2] <= Mux~18.DB_MAX_OUTPUT_PORT_TYPE
dataout3[3] <= Mux~17.DB_MAX_OUTPUT_PORT_TYPE
dataout3[4] <= Mux~16.DB_MAX_OUTPUT_PORT_TYPE
dataout3[5] <= Mux~15.DB_MAX_OUTPUT_PORT_TYPE
dataout3[6] <= Mux~14.DB_MAX_OUTPUT_PORT_TYPE
d[0] => regl[0].DATAIN
d[1] => regl[1].DATAIN
d[2] => regl[2].DATAIN
d[3] => regl[3].DATAIN
d[4] => regl[4].DATAIN
d[5] => regl[5].DATAIN
d[6] => regl[6].DATAIN
d[7] => regl[7].DATAIN
clk => count[30].CLK
clk => count[29].CLK
clk => count[28].CLK
clk => count[27].CLK
clk => count[26].CLK
clk => count[25].CLK
clk => count[24].CLK
clk => count[23].CLK
clk => count[22].CLK
clk => count[21].CLK
clk => count[20].CLK
clk => count[19].CLK
clk => count[18].CLK
clk => count[17].CLK
clk => count[16].CLK
clk => count[15].CLK
clk => count[14].CLK
clk => count[13].CLK
clk => count[12].CLK
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => t.CLK
clk => count11[31].CLK
clk => count11[30].CLK
clk => count11[29].CLK
clk => count11[28].CLK
clk => count11[27].CLK
clk => count11[26].CLK
clk => count11[25].CLK
clk => count11[24].CLK
clk => count11[23].CLK
clk => count11[22].CLK
clk => count11[21].CLK
clk => count11[20].CLK
clk => count11[19].CLK
clk => count11[18].CLK
clk => count11[17].CLK
clk => count11[16].CLK
clk => count11[15].CLK
clk => count11[14].CLK
clk => count11[13].CLK
clk => count11[12].CLK
clk => count11[11].CLK
clk => count11[10].CLK
clk => count11[9].CLK
clk => count11[8].CLK
clk => count11[7].CLK
clk => count11[6].CLK
clk => count11[5].CLK
clk => count11[4].CLK
clk => count11[3].CLK
clk => count11[2].CLK
clk => count11[1].CLK
clk => count11[0].CLK
clk => t1.CLK
clk => count[31].CLK
eoc => next_state.st3.IN3
eoc => next_state.st5.DATAB
eoc => next_state.st4.IN1
clk1 <= t1.DB_MAX_OUTPUT_PORT_TYPE
start <= current_state.st2.DB_MAX_OUTPUT_PORT_TYPE
ale <= current_state.st1.DB_MAX_OUTPUT_PORT_TYPE
en <= en~0.DB_MAX_OUTPUT_PORT_TYPE
abc_in[0] => Mux~21.IN10
abc_in[0] => Mux~22.IN10
abc_in[0] => Mux~23.IN10
abc_in[0] => Mux~24.IN10
abc_in[0] => Mux~25.IN10
abc_in[0] => Mux~26.IN10
abc_in[0] => Mux~27.IN10
abc_in[0] => abc_out[0].DATAIN
abc_in[1] => Mux~21.IN9
abc_in[1] => Mux~22.IN9
abc_in[1] => Mux~23.IN9
abc_in[1] => Mux~24.IN9
abc_in[1] => Mux~25.IN9
abc_in[1] => Mux~26.IN9
abc_in[1] => Mux~27.IN9
abc_in[1] => abc_out[1].DATAIN
abc_in[2] => Mux~21.IN8
abc_in[2] => Mux~22.IN8
abc_in[2] => Mux~23.IN8
abc_in[2] => Mux~24.IN8
abc_in[2] => Mux~25.IN8
abc_in[2] => Mux~26.IN8
abc_in[2] => Mux~27.IN8
abc_in[2] => abc_out[2].DATAIN
abc_out[0] <= abc_in[0].DB_MAX_OUTPUT_PORT_TYPE
abc_out[1] <= abc_in[1].DB_MAX_OUTPUT_PORT_TYPE
abc_out[2] <= abc_in[2].DB_MAX_OUTPUT_PORT_TYPE
q[0] <= regl[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= regl[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= regl[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= regl[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= regl[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= regl[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= regl[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= regl[7].DB_MAX_OUTPUT_PORT_TYPE
dataout4[0] <= Mux~27.DB_MAX_OUTPUT_PORT_TYPE
dataout4[1] <= Mux~26.DB_MAX_OUTPUT_PORT_TYPE
dataout4[2] <= Mux~25.DB_MAX_OUTPUT_PORT_TYPE
dataout4[3] <= Mux~24.DB_MAX_OUTPUT_PORT_TYPE
dataout4[4] <= Mux~23.DB_MAX_OUTPUT_PORT_TYPE
dataout4[5] <= Mux~22.DB_MAX_OUTPUT_PORT_TYPE
dataout4[6] <= Mux~21.DB_MAX_OUTPUT_PORT_TYPE