adc0809.vhd

实现对ad的控制并用7279芯片进行显示

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ADC0809 is
  port ( 
      RST_N     :IN	STD_LOGIC;  --系统复位
dataout1,dataout2,dataout3 	  :  OUT  STD_LOGIC_VECTOR(6 downto 0); 
       d       : in std_logic_vector(7 downto 0);          --ADC0809输出的采样数据
     clk,eoc   : in std_logic;        --clk为系统时钟，eoc为ADC0809转换结束信号
clk1,start, ale,en: out std_logic;                                --ADC0809控制信号
     abc_in    :in std_logic_vector(2 downto 0);                     --模拟选通信号
   
abc_out     :out std_logic_vector(2 downto 0);        --ADC0809模拟信号选通信号

    --   A_BUS   :OUT  STD_LOGIC_VECTOR(2 downto 0);   --地址信号, 0为数据信号, 1为命令字
      
     --  D_BUS   :OUT  STD_LOGIC_VECTOR(7 downto 0);  --指令,数据输入及键盘值输出
        q      : out std_logic_vector(7 downto 0);
    dataout4	  :  OUT  STD_LOGIC_VECTOR(6 downto 0));          --送至8个并排数码管信号
 end ADC0809; 
architecture behav of ADC0809 is 
type states is ( st0,st1, st2, st3, st4,st5,st6);                         --定义各状态的子类型
signal current_state, next_state:states:=st0;
signal regl :std_logic_vector(7 downto 0);                            --中间数据寄存信号
signal qq:std_logic_vector(7 downto 0);
signal t,t1,temp : STD_LOGIC;
signal count,count11: integer ; 
signal cp2: STD_LOGIC;  --分频后的时钟
signal temp1:integer range 511 downto 0;
signal temp2:integer range 99 downto 0;
signal count1,count2,count4:integer range 9 downto 0;
signal count3:integer range 5 downto 0;
signal dp		: std_logic; 

begin
com:process(current_state,eoc)                             --规定各种状态的转换方式
begin
  case current_state is
  when st0=>next_state<=st1;ale<='0';start<='0';en<='0';
  when st1=>next_state<=st2;ale<='1';start<='0';en<='0';
  when st2=>next_state<=st3;ale<='0';start<='1';en<='0';
  when st3=>             ale<='0';start<='0';en<='0';
        if eoc='1' then next_state<=st3;                            --检测EOC的下降沿
        else next_state<=st4;
        end if;    
  when st4=>              ale<='0';start<='0';en<='0';
        if eoc='0' then next_state<=st4;                            --检测EOC的上升沿
        else next_state<=st5;
       end if;
  when st5=>next_state<=st6;ale<='0';start<='0';en<='1';
  when st6=>next_state<=st0;ale<='0';start<='0';en<='1';regl<=d;
  when others=> next_state<=st0;ale<='0';start<='0';en<='0';
  end case;
end process;




p1: process(clk)                    ----分频

begin
if (clk'event and clk='1') then
if (count =4) then
count<= 0;
t <= not t;
else
count<= count + 1;
end if;
end if;
cp2<=t;
end process p1;

p3: process(clk)
begin
if (clk'event and clk='1') then
if (count11 =50) then
count11<= 0;
t1<= not t1;
else
count11<= count11 + 1;
end if;
end if;
clk1<=t1;
end process p3;

p2:process(cp2,RST_N)
begin
if(RST_N='0')  then
   current_state<=st0;count1<=0;count2<=0;count3<=0;
elsif(cp2'event and cp2='1') then
   current_state <=next_state;    

end if;

q<=regl; 



temp1<=conv_integer(regl)+conv_integer(regl);
case temp1 is
  when  500 to 511=>count3<=5;temp2<=temp1-500;
  when  400 to 499=>count3<=4;temp2<=temp1-400;  
  when  300 to 399=>count3<=3;temp2<=temp1-300;
  when  200 to 299=>count3<=2;temp2<=temp1-200;
  when  100 to 199=>count3<=1;temp2<=temp1-100;
  when  0 to 99=>count3<=0;temp2<=temp1;
  when  others=>null;
end case;

case temp2 is
  when 90 to  99=>count2<=9;count1<=temp2-90;
  when 80 to  89=>count2<=8;count1<=temp2-80;
  when 70 to  79=>count2<=7;count1<=temp2-70;
  when 60 to  69=>count2<=6;count1<=temp2-60;
  when 50 to  59=>count2<=5;count1<=temp2-50;
  when 40 to  49=>count2<=4;count1<=temp2-40;
  when 30 to  39=>count2<=3;count1<=temp2-30;
  when 20 to  29=>count2<=2;count1<=temp2-20;

  when 10 to  19=>count2<=1;count1<=temp2-10;
  when 0 to  9=>count2<=0;count1<=temp2;
    when  others=>null;
end case;

 case count1 is
   when 0=>dataout1<="1111110";
   when 1=>dataout1<="0110000";
   when 2=>dataout1<="1101101";
   when 3=>dataout1<="1111001";
   when 4=>dataout1<="0110011";
   when 5=>dataout1<="1011011";
   when 6=>dataout1<="1011111";
   when 7=>dataout1<="1110000";
   when 8=>dataout1<="1111111";
   when 9=>dataout1<="1111011";
 when others=>null;
end case;

 case count2 is
   when 0=>dataout2<="1111110";
   when 1=>dataout2<="0110000";
   when 2=>dataout2<="1101101";
   when 3=>dataout2<="1111001";
   when 4=>dataout2<="0110011";
   when 5=>dataout2<="1011011";
   when 6=>dataout2<="1011111";
   when 7=>dataout2<="1110000";
   when 8=>dataout2<="1111111";
   when 9=>dataout2<="1111011";
 when others=>null;
end case;
  case count3 is
  when 0=>dataout3<="1111110";
   when 1=>dataout3<="0110000";
   when 2=>dataout3<="1101101";
   when 3=>dataout3<="1111001";
   when 4=>dataout3<="0110011";
   when 5=>dataout3<="1011011";
when others=>null;
end case;
   case abc_in is
  when "000"=>dataout4<="1111110";
   when "001"=>dataout4<="0110000";
   when "010"=>dataout4<="1101101";
   when "011"=>dataout4<="1111001";
   when "100"=>dataout4<="0110011";
   when "101"=>dataout4<="1011011";
   when "110"=>dataout4<="1011111";
   when "111"=>dataout4<="1110000";
when others=>null;
end case;
end process p2;
abc_out<=abc_in; 
END BEHAV;