8.qsf

实现对ad的控制并用7279芯片进行显示

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		8_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:48:17  MAY 04, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2"
set_global_assignment -name VHDL_FILE hd7279.vhd
set_global_assignment -name VHDL_FILE adc0809.vhd
set_global_assignment -name BDF_FILE 8.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE 8.vwf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_153 -to clk
set_location_assignment PIN_8 -to clk1
set_location_assignment PIN_156 -to clk7279
set_location_assignment PIN_132 -to cs7279
set_location_assignment PIN_105 -to d\[0\]
set_location_assignment PIN_104 -to d\[1\]
set_location_assignment PIN_101 -to d\[2\]
set_location_assignment PIN_100 -to d\[3\]
set_location_assignment PIN_85 -to d\[4\]
set_location_assignment PIN_84 -to d\[5\]
set_location_assignment PIN_83 -to d\[6\]
set_location_assignment PIN_82 -to d\[7\]
set_location_assignment PIN_158 -to dat7279
set_location_assignment PIN_38 -to en
set_location_assignment PIN_28 -to eoc
set_location_assignment PIN_131 -to RST_N
set_location_assignment PIN_39 -to ale
set_location_assignment PIN_128 -to channel\[0\]
set_location_assignment PIN_115 -to channel\[1\]
set_location_assignment PIN_114 -to channel\[2\]
set_location_assignment PIN_159 -to key7279

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY 8

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C12Q240C8
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF

set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"