xllp_usbohci.h

Intel PXA270底层设备驱动代码

#define	XLLP_USBOHCI_UHCRHPS_POCI				( 1u   << 3 )
#define	XLLP_USBOHCI_UHCRHPS_PRS				( 1u   << 4 )

#define	XLLP_USBOHCI_UHCRHPS_PPS				( 1u   << 8 )

#define	XLLP_USBOHCI_UHCRHPS_LSDA				( 1u   << 9 )		// meaning on read
#define	XLLP_USBOHCI_UHCRHPS_CPP				( 1u   << 9 )		// Write 1 to clear

#define	XLLP_USBOHCI_UHCRHPS_CSC				( 1u   << 16 )
#define	XLLP_USBOHCI_UHCRHPS_PESC				( 1u   << 17 )
#define	XLLP_USBOHCI_UHCRHPS_PSSC				( 1u   << 18 )
#define	XLLP_USBOHCI_UHCRHPS_POCIC				( 1u   << 19 )
#define	XLLP_USBOHCI_UHCRHPS_PRSC				( 1u   << 20 )

// fields and bits for UHCSTAT:		UHC Status register
// All UHCSTAT bits below are Write 1 to clear
#define	XLLP_USBOHCI_UHCSTAT_RWUE				( 1u   << 7 )
#define	XLLP_USBOHCI_UHCSTAT_HBA				( 1u   << 8 )
#define	XLLP_USBOHCI_UHCSTAT_HTA				( 1u   << 10 )
#define	XLLP_USBOHCI_UHCSTAT_UPS1				( 1u   << 11 )
#define	XLLP_USBOHCI_UHCSTAT_UPS2				( 1u   << 12 )
#define	XLLP_USBOHCI_UHCSTAT_UPRI				( 1u   << 13 )
#define	XLLP_USBOHCI_UHCSTAT_SBTAI				( 1u   << 14 )
#define	XLLP_USBOHCI_UHCSTAT_SBMAI				( 1u   << 15 )
#define	XLLP_USBOHCI_UHCSTAT_UPS3				( 1u   << 16 )

#define P_XLLP_USBOHCI_UHCSTAT( pUsbhHandle ) ((pUsbhHandle)->pUSBHRegs->UHCSTAT)

// Mask for write 1 to clear bits in UHCSTAT
#define XLLP_USBOHCI_UHCSTAT_MASK  (0xFFFFFFFF)
//#define XLLP_USBOHCI_UHCSTAT_MWRITE( pUsbhHandle, y )  (P_XLLP_USBOHCI_UHCSTAT( pUsbhHandle ) = (((P_XLLP_USBOHCI_UHCSTAT( pUsbhHandle )) & (~XLLP_USBOHCI_UHCSTAT_MASK)) | y))
////Optimized:
//#define XLLP_USBOHCI_UHCSTAT_MWRITE( pUsbhHandle, y )    ((P_XLLP_USBOHCI_UHCSTAT( pUsbhHandle )) = (y))
#define XLLP_USBOHCI_UHCSTAT_MWRITE( pUsbhHandle, y )    (((pUsbhHandle)->pUSBHRegs->UHCSTAT) = (y))
//To invoke, call:
//XLLP_USBOHCI_UHCSTAT_MWRITE( pUsbhHandle, y)  

// fields and bits for UHCHR:		UHC Reset register

#define XLLP_USBOHCI_UHCHR_FSBIR				( 1u <<  0)	// Force System Bus Interface Reset: When 1, resets the logic that interfaces to the system bus, DMA, etc. Auto clears after three system bus clocks.
#define	XLLP_USBOHCI_UHCHR_FHR					( 1u <<  1)	// Force Host controller Reset: When 1, resets OHCI core. Must be held high for 10 uSeconds, then cleared
#define XLLP_USBOHCI_UHCHR_CGR					( 1u <<  2)	// Clock Generation Reset: When 0, resets the OHCI Clock Generation block (DPLL). Used only in simulation
#define XLLP_USBOHCI_UHCHR_SSDC					( 1u <<  3)	// Simulation Scale Down Clock: When 1, internal 1 mSec timer changes to 1 uSec to speed up simulations
#define XLLP_USBOHCI_UHCHR_UIT					( 1u <<  4)	// USB Interrupt Test: Enable Interrupt Test Mode and UHCHIT register
#define XLLP_USBOHCI_UHCHR_SSE					( 1u <<  5)	// Sleep Standby Enable: enable/disable both ports SE receivers & power  supply
#define XLLP_USBOHCI_UHCHR_PSPL					( 1u <<  6)	// Power SENSE Polarity: Control polarity of Over-current Indicator signals input from the MAX1693EUB USB Power Switch
#define XLLP_USBOHCI_UHCHR_PCPL					( 1u <<  7)	// Power CONTROL Polarity: Control polarity of Power Enable signals output to the MAX1693EUB USB Power Switch
#define XLLP_USBOHCI_UHCHR_SSEP1				( 1u <<  9)	// Sleep Standby Enable: enable/disable port1 SE receivers & power supply
#define XLLP_USBOHCI_UHCHR_SSEP2				( 1u << 10)	// Sleep Standby Enable: enable/disable port2 SE receivers & power supply
#define XLLP_USBOHCI_UHCHR_SSEP3				( 1u << 11)	// Sleep Standby Enable: enable/disable port3 SE receivers & power supply


// fields and bits for UHCHIE:		UHC Interrupt Enable register
#define	XLLP_USBOHCI_UHCHIE_RWIE				( 1u   << 7 )
#define	XLLP_USBOHCI_UHCHIE_HBAIE				( 1u   << 8 )
#define	XLLP_USBOHCI_UHCHIE_TAIE				( 1u   << 10 )
#define	XLLP_USBOHCI_UHCHIE_UPS1IE				( 1u   << 11 )
#define	XLLP_USBOHCI_UHCHIE_UPS2IE				( 1u   << 12 )
#define	XLLP_USBOHCI_UHCHIE_UPRIE				( 1u   << 13 )
#define	XLLP_USBOHCI_UHCHIE_UPS3IE				( 1u   << 14 )


// fields and bits for UHCHIT:		USB Host Interrupt Test register
#define	XLLP_USBOHCI_UHCHIT_RWUT				( 1u   << 7 )
#define	XLLP_USBOHCI_UHCHIT_BAT					( 1u   << 8 )
#define	XLLP_USBOHCI_UHCHIT_IRQT				( 1u   << 9 )
#define	XLLP_USBOHCI_UHCHIT_TAT					( 1u   << 10 )
#define	XLLP_USBOHCI_UHCHIT_UPS1T				( 1u   << 11 )
#define	XLLP_USBOHCI_UHCHIT_UPS2T				( 1u   << 12 )
#define	XLLP_USBOHCI_UHCHIT_UPRT				( 1u   << 13 )
#define	XLLP_USBOHCI_UHCHIT_STAT				( 1u   << 14 )
#define	XLLP_USBOHCI_UHCHIT_SMAT				( 1u   << 15 )
#define	XLLP_USBOHCI_UHCHIT_UPS3T				( 1u   << 16 )


// Port Power Managment Modes
enum {
	XLLP_USBOHCI_PPM_NPS,
	XLLP_USBOHCI_PPM_GLOBAL,
	XLLP_USBOHCI_PPM_PERPORT,
	XLLP_USBOHCI_PPM_MIXED
};


typedef struct XLLP_USBH_HANDLE_S 
{
   P_XLLP_USBOHCI_T  pUSBHRegs;    // Pointer to USB Host registers
   P_XLLP_GPIO_T   pGPIORegs;      // Pointer to the GPIO registers
   P_XLLP_BCR_T    pBLRRegs;       // Pointer to the Board Specific registers
   P_XLLP_CLKMGR_T pCLKMGRRegs;    // Pointer to the Clock Manager registers
   P_XLLP_OST_T pOSTRegs;          // Pointer to OST registers
   P_XLLP_PLATFORM_USBH_T pPlatformUSBHConfig ; //Pointer to Platform Specific USBH Configuration

} XLLP_USBH_HANDLE_T, *P_XLLP_USBH_HANDLE_T;


typedef enum _XLLP_USBH_ERROR_T {
     
    XLLP_USBH_SUCCESS = 0,
	XLLP_USBH_GPIO_POINTER_NULL,
	XLLP_USBH_CONTROLLER_POINTER_NULL,
	XLLP_USBH_BLR_POINTER_NULL,
	XLLP_USBH_CLKMGR_POINTER_NULL,
	XLLP_USBH_OST_POINTER_NULL, 
	XLLP_USBH_FEATURE_NOT_SUPPORTED

}XLLP_USBH_ERROR_T;

typedef enum _XLLP_USBH_PORT_T {
     
    XLLP_USBH_PORT_1 = 1,
	XLLP_USBH_PORT_2,
	XLLP_USBH_PORT_3

}XLLP_USBH_PORT_T;

/*
************************************************************************************
*                            FUNCTION PROTOTYPES 
************************************************************************************
*/



//Chip specific:

XLLP_USBH_ERROR_T XllpUsbhReset(P_XLLP_USBH_HANDLE_T pUsbhHandle);

XLLP_USBH_ERROR_T XllpUsbhSelectPowerManagementMode (
								   P_XLLP_USBH_HANDLE_T pUsbhHandle , 
								   XLLP_UINT32_T  PowerMode,                           
                                   XLLP_UINT32_T  NumPorts, 
                                   P_XLLP_UINT32_T  pPortMode) ;

XLLP_USBH_ERROR_T XllpUsbhPowerUp(P_XLLP_USBH_HANDLE_T pUsbhHandle);

XLLP_USBH_ERROR_T XllpUsbhPowerDown(P_XLLP_USBH_HANDLE_T pUsbhHandle);


__inline XLLP_USBH_ERROR_T XllpUsbhTurnOnUSBHostClock(P_XLLP_USBH_HANDLE_T pUsbhHandle)
{
	// The clock enable bit for the USB Host OHCI block in PXA27x
	// is bit 10.
	
	pUsbhHandle->pCLKMGRRegs->cken |= XLLP_CLKEN_USBHOST;

    return (XLLP_USBH_SUCCESS);
}


__inline XLLP_USBH_ERROR_T XllpUsbhTurnOnSRAMClock(P_XLLP_USBH_HANDLE_T pUsbhHandle)
{
	
	// The clock enable bit for the Internal SRAM in PXA27x
	// is bit 20.
	pUsbhHandle->pCLKMGRRegs->cken |= XLLP_CLKEN_MEMCLOCK ;

    return (XLLP_USBH_SUCCESS);
}

__inline XLLP_USBH_ERROR_T XllpUsbhTurnOffUSBHostClock(P_XLLP_USBH_HANDLE_T pUsbhHandle)
{
	// The clock enable bit for the USB Host OHCI block in PXA27x
	// is bit number 10.
	pUsbhHandle->pCLKMGRRegs->cken &= ~XLLP_CLKEN_USBHOST;

    return (XLLP_USBH_SUCCESS);
}


//Platform Specific:


extern XLLP_USBH_ERROR_T XllpUsbhPortEnableOverCurrentNotification(P_XLLP_USBH_HANDLE_T pUsbhHandle,XLLP_USBH_PORT_T Port);

extern XLLP_USBH_ERROR_T XllpUsbhPortEnablePower(P_XLLP_USBH_HANDLE_T pUsbhHandle, XLLP_USBH_PORT_T Port); 

extern XLLP_USBH_ERROR_T XllpUsbhInitPlatformSpecificConfig(P_XLLP_USBH_HANDLE_T pUsbhHandle);

extern XLLP_USBH_ERROR_T XllpUsbhConfigPlatformSpecificUSBHReset(P_XLLP_USBH_HANDLE_T pUsbhHandle);

XLLP_USBH_ERROR_T XllpUsbhPortEnableSleepStandbyEnable(P_XLLP_USBH_HANDLE_T pUsbhHandle, 
													   XLLP_USBH_PORT_T Port, 
													   XLLP_BOOL_T enable);


__inline XLLP_USBH_ERROR_T XllpUsbhConfigureGlobalSleepStandbyEnable(P_XLLP_USBH_HANDLE_T pUsbhHandle, 
																  XLLP_BOOL_T enable)
{
	if (XLLP_TRUE == enable)
    {
      pUsbhHandle->pUSBHRegs->UHCHR &= ~XLLP_USBOHCI_UHCHR_SSE;
	}
	else
	{
	  pUsbhHandle->pUSBHRegs->UHCHR |= XLLP_USBOHCI_UHCHR_SSE;
	}

    return (XLLP_USBH_SUCCESS);
}



__inline XLLP_USBH_ERROR_T XllpUsbhConfigurePowerSensePolarity(P_XLLP_USBH_HANDLE_T pUsbhHandle, 
													  XLLP_LEVEL_T level)
{
	if (XLLP_HI == level)
    {
      pUsbhHandle->pUSBHRegs->UHCHR &= ~XLLP_USBOHCI_UHCHR_PSPL;
	}
	else
	{
	  pUsbhHandle->pUSBHRegs->UHCHR |= XLLP_USBOHCI_UHCHR_PSPL;
	}

    return (XLLP_USBH_SUCCESS);
}


__inline XLLP_USBH_ERROR_T XllpUsbhConfigurePowerControlPolarity(
														P_XLLP_USBH_HANDLE_T pUsbhHandle, 
													    XLLP_LEVEL_T level)
{
	if (XLLP_HI == level)
    {
      pUsbhHandle->pUSBHRegs->UHCHR &= ~XLLP_USBOHCI_UHCHR_PCPL;
	}
	else
	{
	  pUsbhHandle->pUSBHRegs->UHCHR |= XLLP_USBOHCI_UHCHR_PCPL;
	}

    return (XLLP_USBH_SUCCESS);
}




#ifdef __cplusplus
}
#endif


#endif //__XLLP_USBHOST_H__